External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

8. Arria® 10 EMIF IP for QDR II/II+/II+ Xtreme

This chapter contains IP parameter descriptions, board skew equations, pin planning information, and board design guidance for Arria® 10 external memory interfaces for QDR II/II+/II+ Xtreme.