External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

3.1.2. I/O Column

Arria® 10 devices have two I/O columns which contain the hardware related to external memory interfaces.
Each I/O column contains the following major parts:
  • A hardened Nios processor with dedicated memory. This Nios block is referred to as the I/O AUX.
  • Up to 13 I/O banks. Each I/O bank contains the hardware necessary for an external memory interface.
Figure 3. I/O Column