External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

3.9. Arria® 10 EMIF and SmartVID

The external memory interface IP can work with the SmartVID voltage management system, to achieve reduced power consumption.
Note: Arria® 10 HPS EMIF IP does not currently support SmartVID.

The SmartVID controller allows the FPGA to operate at a reduced Vcc, while maintaining performance. Because the SmartVID controller can adjust Vcc up or down in response to power requirements and temperature, it can have an impact on external memory interface performance. When used with the SmartVID controller, the EMIF IP implements a handshake protocol to ensure that EMIF calibration does not begin until after voltage adjustment has completed.

In extended speed grade devices, voltage adjustment occurs once when the FPGA is powered up, and no further voltage adjustments occur. The external memory calibration occurs after this initial voltage adjustment is completed. EMIF specifications are expected to be slightly lower in extended speed grade devices using SmartVID, than in devices not using SmartVID.

In industrial speed grade devices, voltage adjustment occurs at power up, and may also occur during operation, in response to temperature changes. External memory interface calibration does not occur until after the initial voltage adjustment at power up. However, the external memory interface is not recalibrated in response to subsequent voltage adjustments that occur during operation. As a result, EMIF specifications for industrial speed grade devices using SmartVID are expected to be lower than for extended speed grade devices.

Using the EMIF IP with SmartVID

To use your EMIF IP with SmartVID, follow these steps:

  1. Ensure that the Quartus® Prime project and Platform Designer system are configured to use VID components. This step exposes the vid_cal_done_persist interface on instantiated EMIF IP, which is required for communicating with the SmartVID controller.
  2. Instantiate the SmartVID controller, using an I/O PLL IP core to drive the 125MHz vid_clk and the 25MHz jtag_core_clk inputs of the Smart VID controller.
    Note: Do not connect the emif_usr_clk signal to either the vid_clk or jtag_core_clk inputs. Doing so would hold both the EMIF IP and the SmartVID controller in a perpetual reset condition.
  3. Instantiate the EMIF IP.
  4. Connect the vid_cal_done_persist signal from the EMIF IP with the cal_done_persistent signal on the SmartVID controller. This connection enables handshaking between the EMIF IP and the SmartVID controller, which allows the EMIF IP to delay memory calibration until after voltage levels are stabilized.
    Note: The EMIF vid_cal_done_persist interface becomes available only when a VID-enabled device is selected.