External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

3.3. Arria® 10 EMIF Calibration

The calibration process compensates for skews and delays in the external memory interface.

The calibration process enables the system to compensate for the effects of factors such as the following:

  • Timing and electrical constraints, such as setup/hold time and Vref variations.
  • Circuit board and package factors, such as skew, fly-by effects, and manufacturing variations.
  • Environmental uncertainties, such as variations in voltage and temperature.
  • The demanding effects of small margins associated with high-speed operation.

For a given external memory interface, calibration occurs in parallel for all DQS groups and I/O banks. For an I/O column containing multiple external memory interfaces, there is no particular calibration order in relation to the interfaces; however, for a given SRAM Object File (.sof), calibration will always occur in the same order.