Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 7/08/2024
Public
Document Table of Contents

6.4. Parameterizing Native Fixed Point DSP IP Core

  1. In Quartus® Prime Pro Edition, create a new project that targets a Stratix® 10 device.
  2. In IP Catalog, click Library > DSP > Primitive DSP > Native Fixed Point DSP .
    The Native Fixed Point DSP IP Core IP parameter editor opens.
  3. In the New IP Variation dialog box, enter an Entity Name and click OK.
  4. Under Parameters, select the operation mode, multiplier configuration, clear signal, port width, and internal coefficient configurations according to the variant of your IP core
  5. In the DSP Block View, switch the clock of each valid register.
  6. Click the input and output ports in the GUI to select your desired inputs and outputs.
  7. Click the Preadder symbols in the GUI to select addition or subtraction.
  8. Click the Top delay register Bottom delay register and symbols in the GUI to enable the delay registers.
  9. Click the multiplexer symbols in the GUI to enable the preadder modules and the internal coefficient modules.
  10. Click the clken port symbols to create clock enable signal for each valid register.
  11. Click the clr port symbols to create clear signal for each valid register.
  12. Click Generate HDL.
  13. Click Finish.