Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

3.1.5.3. 27-Bit Systolic FIR Mode

In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing 10 bits of overhead when using a 27-bit data (54-bit products).

The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block. Systolic registers are not required in this mode.

Figure 16.  27-Bit Systolic FIR Mode for Intel® Stratix® 10 Devices

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