Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

13. Document Revision History for the Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.08.13 21.2
  • Added the DSP Block Cascade Limit in Intel® Stratix® 10 Devices topic.
  • Removed the statements about the number of DSP blocks you can cascade as systolic FIR structure in the following topics:
    • 18-bit Systolic FIR Mode
    • 27-Bit Systolic FIR Mode
  • In the 27-Bit Systolic FIR Mode topic, removed the "Systolic registers are not required in this mode" statement. The registers are not available in the 27-bit systolic FIR mode.
2020.09.28 20.3
  • Added the X Input Value Support In Simulation topic to describes input signals supporting X value in simulation.
  • Added notes to the input signals of the following IPs regarding the X value propagation support in simulation:
    • Native Fixed Point DSP Intel® Stratix® 10 FPGA IP
    • Multiply Adder IP
    • ALTMULT_COMPLEX Intel FPGA IP
    • LPM_MULT Intel FPGA IP
    • Native Floating Point DSP Intel® Stratix® 10 FPGA IP
2020.04.26 19.3
  • Updated values for Which multiplier implementation should be used? parameter for the LPM_MULT IP core.
2019.10.22 19.3
  • Updated number of multipliers for Intel® Stratix® 10 TX 400, DX 1100, DX 2100, and DX 2800 devices in Resources section.
  • Added IP release information for:
    • Native Fixed Point DSP Intel® Stratix® 10 version 19.1.0
    • ALTMULT_COMPLEX Intel FPGA IP version 19.1.0
    • Multiply Adder Intel FPGA IP version 19.1.0
    • LPM_MULT Intel FPGA IP version 19.1.0
    • Native Floating Point DSP Intel® Stratix® 10 version 19.1.0
  • Added information about LPM_DIVIDE Intel FPGA IP version 19.1.
  • Updated input and output register bank reset behavior in Input Register Bank for Fixed-point and Floating-point Arithmetic and Output Register Bank for Fixed-point Arithmetic topics.
2018.09.24 18.1
  • Updated resource count for device GX 1100, SX 1100, and MX 1100 in Number of Multipliers in Intel® Stratix® 10 Devices table.
2018.05.07 18.0
  • Updated default value for How wide should result scanout width? parameter in General Parameters table for Native Fixed Point DSP Intel® Stratix® 10 FPGA IP core.
  • Added What is the value for loadconst? parameter in Coefficient Configuration table for Native Fixed Point DSP Intel® Stratix® 10 FPGA IP core.
  • Added a footnote to the supported operation instance for the fixed-point independent 18 x 19 multiplication operation mode in the Supported Combinations of Operational Modes and Features for Variable Precision DSP Block in the Intel® Stratix® 10 Devices table.
  • Added the subtract feature in the Fixed-Point Arithmetic DSP Implementation in the Block Architecture table.
  • Added subtractor to the one-point floating arithmetic in the Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic section.
  • Added the Enable double accumulator parameter in the Accumulator Tab table.
  • Updated the figure title of the One Sum of Two 18 x 18 or 18 x 19 Multipliers with One Variable Precision DSP Block for Intel® Stratix® 10 Devices.
  • Minor editorial edits.
  • Updated all IP names as per Intel rebranding.
Date Version Changes
November 2017 2017.11.06
  • Updated resource count for Intel® Stratix® 10 MX and TX variants.
  • Updated Maximum Input Data Width for Fixed-Point Arithmetic.
  • Introduced new m18x18_full_top operation mode in Native Fixed Point DSP IP core.
  • Updated systolic registers implementation guidelines.
  • Added note to clarify the floating-point exception handling flags are referring to output value exceptions in Multiplier Exception Handling Possible Results and Adder Exception Handling Possible Results tables.
  • Updated description for exception handling flags in Multiplier Exception Handling Possible Results and Adder Exception Handling Possible Results tables.
  • Updated Native Fixed Point DSP Parameter settings with DSP Block View description.
  • Rebranded ALTERA_MULT_ADD IP core to Multiply Adder.
  • Removed aclr[1:0] signal from Native Floating Point DSP Intel Stratix 10 FPGA IP core.
May 2017 2017.05.08 Updated the behavior description of the sload_accum and accum_sload signals in the ALTERA_MULT_ADD Input Signals table.
October 2016 2016.10.31 Initial release.

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