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1. Stratix® 10 Variable Precision DSP Blocks Overview
2. Block Architecture Overview
3. Operational Mode Descriptions
4. Design Considerations
5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide
6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References
7. Multiply Adder IP Core References
8. ALTMULT_COMPLEX Intel® FPGA IP Core References
9. LPM_MULT Intel® FPGA IP Core References
10. Native Floating Point DSP Stratix® 10 FPGA IP References
11. LPM_DIVIDE (Divider) Intel FPGA IP Core
12. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives
13. Document Revision History for the Stratix® 10 Variable Precision DSP Blocks User Guide
2.1. Input Register Bank for Fixed-Point and Floating-Point Arithmetic
2.2. Pipeline Registers for Fixed-Point and Floating-Point Arithmetic
2.3. Pre-adder for Fixed-Point Arithmetic
2.4. Internal Coefficient for Fixed-Point Arithmetic
2.5. Multipliers for Fixed-Point and Floating-Point Arithmetic
2.6. Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic
2.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic
2.8. Systolic Register for Fixed-Point Arithmetic
2.9. Double Accumulation Register for Fixed-Point Arithmetic
2.10. Output Register Bank for Fixed-Point and Floating-Point Arithmetic
2.11. Exception Handling for Floating-Point Arithmetic
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2.10. Output Register Bank for Fixed-Point and Floating-Point Arithmetic
The positive edge of the clock signal triggers the 74-bit bypassable output register bank. The output register bank is not reset after power up and may hold unwanted data. Assert the CLR signal to clear the register before starting an operation.
The following variable precision DSP block signals control the output register per variable precision DSP block:
- CLK[2..0]
- ENA[2..0]
- CLR[1]