Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

9.4. Signals

Table 53.   LPM_MULT Intel® FPGA IP Core Input SignalsThe simulation model for this IP supports undetermined input value (X) to the following signals. When you provide X value to these signals, the X value is propagated on the output signals.
Signal Name Required Description
dataa[] Yes Data input.

The size of the input signal depends on the Dataa width parameter value.

datab[] Yes Data input.

The size of the input signal depends on the Datab width parameter value.

clock No Clock input for pipelined usage.

For Latency values other than 1 (default), the clock signal must be enabled.

clken No Clock enable for pipelined usage. When the clken signal is asserted high, the adder/subtractor operation takes place. When the signal is low, no operation occurs. If omitted, the default value is 1.
aclr No Asynchronous clear signal used at any time to reset the pipeline to all 0s, asynchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value.
sclr No Synchronous clear signal used at any time to reset the pipeline to all 0s, synchronously to the clock signal. The pipeline initializes to an undefined (X) logic level. The outputs are a consistent, but non-zero value.
Table 54.   LPM_MULT Intel® FPGA IP Output signals
signal Name Required Description
result[] Yes Data output.

The size of the output signals depends on the Result width parameter.

The simulation model for this IP supports undetermined output value (X). When you provide X value as the input, the X value is propagated on this signal.

Did you find the information on this page useful?

Characters remaining:

Feedback Message