Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

6.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example

This example shows how to configure the Native Fixed Point DSP Intel® Stratix® 10 FPGA IP core to use 18 × 18 Plus 36 operational mode with a signed 12-bit input data of 101010101010 (binary) instead of a 36-bit operand.

  1. Set Representation format for bottom multiplier x operand to signed.
  2. Set Representation format for bottom multiplier y operand to unsigned.
  3. Set 'bx' input bus width to 18.
  4. Set 'by' input bus width to 18.
  5. Provide 18-bit signed representation data, example,'111111111111111111', to bx input bus.
    This step is to perform sign extension. The initial 12 bits input is extended to 36 bits with bx representing the most significant 18 bits.
  6. Provide data 18-bit signed representation data, example, '111111101010101010', to by input bus.

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