Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 7/08/2024
Public
Document Table of Contents

8.2. Features

The ALTMULT_COMPLEX Intel® FPGA IP core offers the following features:

  • Generates a multiplier to perform multiplication operations of two complex numbers
    Note: When building multipliers larger than the natively supported size there may/will be a performance impact resulting from the partial products calculations..
  • Supports data width of 1–256 bits
  • Supports signed and unsigned data representation format
  • Supports pipelining with configurable output latency
  • Supports optional asynchronous and synchronous clear and clock enable input ports