Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

10.3. Parameterizing the Native Floating Point DSP Intel® Stratix® 10 FPGA IP

Select different parameters to create an IP core suitable for your design.
  1. In Intel® Quartus® Prime Pro Edition,create a new project that targets a Intel® Stratix® 10 device.
  2. In IP Catalog, click Library > DSP > Primitive DSP > Native Floating Point DSP Intel® Stratix® 10 FPGA IP.
    The Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core IP parameter editor opens.
  3. In the New IP Variation dialog box, enter an Entity Name and click OK.
  4. Under Parameters, select the DSP Template and the View you want for your IP core
  5. In the DSP Block View, switch the clock or reset of each valid register.
  6. For Multiply Add or Vector Mode 1, click the Chain In multiplexer in the GUI to select input from chainin port or Ax port.
  7. Click the Adder symbol in the GUI to select addition or subtraction.
  8. Click the Chain Out multiplexer in the GUI to enable chainout port.
  9. Click Generate HDL.
  10. Click Finish.

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