Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

2.1. Input Register Bank for Fixed-Point and Floating-Point Arithmetic

The input register banks in Intel® Stratix® 10 DSP blocks are available for the following input signals:
Table 5.  Input Register Bank
Fixed-Point Arithmetic Floating-Point Arithmetic
  • Data
  • Dynamic control signals
    • NEGATE
    • LOADCONST
    • ACCUMULATE
    • SUB
  • Data
  • Dynamic ACCUMULATE control signal

All the registers in the DSP blocks are positive-edge triggered. These registers are not reset after power up and may hold unwanted data. Assert the CLR signal to clear the registers before starting an operation. Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers.

The following variable precision DSP block signals control the input registers within the variable precision DSP block:
  • CLK[2..0]
  • ENA[2..0]
  • CLR[0]
Figure 4. Data Input Registers in Fixed-Point Arithmetic 18 x 19 Mode
Figure 5. Data Input Registers in Fixed-Point Arithmetic 27 x 27 Mode

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