Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

11.7.2. General1 Tab

Parameter Name Value Default Value Description
Pipelining
Output latency 0–14 0 Specifies the number of clock cycles of latency associated with the quotient[] and remain[] outputs. A value of zero (0) indicates that no latency exists, and that a purely combinational function is instantiated. If omitted, the default value is 0 (non-pipelined). You cannot specify a value for the Output latency parameter that is higher than the value specified in the How wide should the 'numerator' input bus be? parameter.
Create an asynchronous Clear input?
  • On
  • Off
Off

Select this option to create aclr signal.

Create a Clock Enable Input?
  • On
  • Off
Off

Select this option to create clken signal for the IP clock.

Optimization
Which do you wish to optimize?
  • Default Optimization
  • Area
  • Speed
Default Optimization Specify type of optimization for a specific instance of the IP.
  • Default Optimization: Select this option to use Intel® Quartus® Prime software to optimize using default optimization technique logic for a specific instance of the IP.
  • Area: Select this option to use Intel® Quartus® Prime software to optimize routability for a specific instance of the IP.
  • Speed: Select this option to use Intel® Quartus® Prime software to optimize speed by using carry chains for a specific instance of the IP.
Remainder
Always return a positive remainder?
  • Yes
  • No
Yes In order to reduce area and improve speed, Intel® recommends setting this parameter to Yes in operations where the remainder must be positive or unimportant.

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