Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

7.3.2. Extra Modes

Table 37.  Extra Modes Tab
Parameter Value Default Value Description
Outputs Configuration
Register output of the adder unit

On

Off

Off

Turn on this option to enable output register of the adder module.

What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to enable and specify the clock source for output registers.

You must select Register output of the adder unit to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the adder output register.

You must select Register output of the adder unit to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the adder output register.

You must select Register output of the adder unit to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

Adder Operation
What operation should be performed on outputs of the first pair of multipliers?

ADD,

SUB,

VARIABLE

ADD

Select addition or subtraction operation to perform for the outputs between the first and second multipliers.

  • Select ADD to perform addition operation.
  • Select SUB to perform subtraction operation.
  • Select VARIABLE to use addnsub1 port for dynamic addition/subtraction control.
When VARIABLE value is selected:
  • Drive addnsub1 signal to high for addition operation.
  • Drive addnsub1 signal to low for subtraction operation.

You must select more than two multipliers to enable this parameter.

Register 'addnsub1' input

On

Off

Off Turn on this option to enable input register for addnsub1 port.

You must select VARIABLE for What operation should be performed on outputs of the first pair of multipliers to enable this parameter.

What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to specify the input clock signal for addnsub1 register.

You must select Register 'addnsub1' input to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the addnsub1 register.

You must select Register 'addnsub1' input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the addnsub1 register.

You must select Register 'addnsub1' input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What operation should be performed on outputs of the second pair of multipliers?

ADD,

SUB,

VARIABLE

ADD

Select addition or subtraction operation to perform for the outputs between the third and fourth multipliers.

  • Select ADD to perform addition operation.
  • Select SUB to perform subtraction operation.
  • Select VARIABLE to use addnsub1 port for dynamic addition/subtraction control.
When VARIABLE value is selected:
  • Drive addnsub1 signal to high for addition operation.
  • Drive addnsub1 signal to low for subtraction operation.

You must select the value 4 for What is the number of multipliers? to enable this parameter.

Register 'addnsub3' input

On

Off

Off Turn on this option to enable input register for addnsub3 signal.

You must select VARIABLE for What operation should be performed on outputs of the second pair of multipliers to enable this parameter.

What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to specify the input clock signal for addnsub3 register.

You must select Register 'addnsub3' input to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the addnsub3 register.

You must select Register 'addnsub3' input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the addnsub3 register.

You must select Register 'addnsub3' input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

Polarity
Enable ‘use_subadd’

On

Off

Off

Turn on this option to reverse the function of addnsub input port.

When this option is turned on, do the following:
  • drive addnsub to high for subtraction operation
  • drive addnsub to low for addition operation

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