Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

1.1. Features

The Intel® Stratix® 10 fixed-point arithmetic features include:

  • High-performance, power-optimized, and fully registered multiplication operations
  • 18-bit and 27-bit word lengths
  • Two 18 x 19 multipliers or one 27 x 27 multiplier per DSP block
  • Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication results
  • Cascading 19-bit or 27-bit and cascading 18-bit when pre-adder is used to form the tap-delay line for filtering applications
  • Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
  • Hard pre-adder supported in 18-bit and 27-bit DSP operation modes for symmetric filters
  • Internal coefficient register bank in both 18-bit and 27-bit modes for filter implementation
  • 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
  • Biased rounding support
The Intel® Stratix® 10 floating-point arithmetic is a completely hardened architecture. Features for floating-point arithmetic include :
  • Multiplication, addition, subtraction, multiply-add, and multiply-subtract
  • Multiplication with accumulation capability and a dynamic accumulator reset control
  • Multiplication with cascade summation and subtraction capability
  • Complex multiplication
  • Direct vector dot product
  • Systolic vector dot product
  • Sequential vector dot product
  • Exception handling support using exception flags

Did you find the information on this page useful?

Characters remaining:

Feedback Message