Stratix® 10 Variable Precision DSP Blocks User Guide

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ID 683832
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Variable Precision DSP Blocks Overview 2. Block Architecture Overview 3. Operational Mode Descriptions 4. Design Considerations 5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide 6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References 7. Multiply Adder IP Core References 8. ALTMULT_COMPLEX Intel® FPGA IP Core References 9. LPM_MULT Intel® FPGA IP Core References 10. Native Floating Point DSP Stratix® 10 FPGA IP References 11. LPM_DIVIDE (Divider) Intel FPGA IP Core 12. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives 13. Document Revision History for the Stratix® 10 Variable Precision DSP Blocks User Guide
1. Stratix® 10 Variable Precision DSP Blocks Overview x
1.1. Features 1.2. Supported Operational Modes in Stratix® 10 Devices 1.3. Resources
2. Block Architecture Overview x
2.1. Input Register Bank for Fixed-Point and Floating-Point Arithmetic 2.2. Pipeline Registers for Fixed-Point and Floating-Point Arithmetic 2.3. Pre-adder for Fixed-Point Arithmetic 2.4. Internal Coefficient for Fixed-Point Arithmetic 2.5. Multipliers for Fixed-Point and Floating-Point Arithmetic 2.6. Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic 2.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic 2.8. Systolic Register for Fixed-Point Arithmetic 2.9. Double Accumulation Register for Fixed-Point Arithmetic 2.10. Output Register Bank for Fixed-Point and Floating-Point Arithmetic 2.11. Exception Handling for Floating-Point Arithmetic
3. Operational Mode Descriptions x
3.1. Operational Modes for Fixed-Point Arithmetic 3.2. Operational Modes for Floating-Point Arithmetic
3.1. Operational Modes for Fixed-Point Arithmetic x
3.1.1. Independent Multiplier Mode 3.1.2. Multiplier Adder Sum Mode 3.1.3. Independent Complex Multiplier 3.1.4. 18 × 19 Multiplication Summed with 36-Bit Input Mode 3.1.5. Systolic FIR Mode
3.1.1. Independent Multiplier Mode x
3.1.1.1. 18 × 18 or 18 × 19 Independent Multiplier 3.1.1.2. 27 × 27 Independent Multiplier
3.1.5. Systolic FIR Mode x
3.1.5.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.1.5.2. 18-bit Systolic FIR Mode 3.1.5.3. 27-Bit Systolic FIR Mode
3.2. Operational Modes for Floating-Point Arithmetic x
3.2.1. Single Floating-Point Arithmetic Functions 3.2.2. Multiple Floating-Point Arithmetic Functions
3.2.1. Single Floating-Point Arithmetic Functions x
3.2.1.1. Multiplication Mode 3.2.1.2. Adder or Subtract Mode 3.2.1.3. Multiply Accumulate Mode
3.2.2. Multiple Floating-Point Arithmetic Functions x
3.2.2.1. Multiply-Add or Multiply-Subtract Mode 3.2.2.2. Vector One Mode 3.2.2.3. Vector Two Mode 3.2.2.4. Direct Vector Dot Product 3.2.2.5. Complex Multiplication
4. Design Considerations x
4.1. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic 4.2. Accumulator for Fixed-Point Arithmetic 4.3. Chainout Adder 4.4. Input Cascade for Fixed-Point Arithmetic 4.5. DSP Block Cascade Limit in Agilex™ 7 Devices
5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide x
5.1. 'X' Propagation Support in Simulation
6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References x
6.1. Native Fixed Point DSP Stratix® 10 FPGA IP Release Information 6.2. Supported Operational Modes 6.3. Maximum Input Data Width for Fixed-Point Arithmetic 6.4. Parameterizing Native Fixed Point DSP IP Core 6.5. Signals
6.3. Maximum Input Data Width for Fixed-Point Arithmetic x
6.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example
6.4. Parameterizing Native Fixed Point DSP IP Core x
6.4.1. Native Fixed Point DSP Stratix® 10 FPGA IP Parameters
7. Multiply Adder IP Core References x
7.1. Multiply Adder Intel FPGA IP Release Information 7.2. Features 7.3. Parameters 7.4. Signals
7.2. Features x
7.2.1. Pre-adder 7.2.2. Systolic Delay Register 7.2.3. Pre-load Constant 7.2.4. Double Accumulator
7.2.1. Pre-adder x
7.2.1.1. Pre-adder Simple Mode 7.2.1.2. Pre-adder Coefficient Mode 7.2.1.3. Pre-adder Input Mode 7.2.1.4. Pre-adder Square Mode 7.2.1.5. Pre-adder Constant Mode
7.3. Parameters x
7.3.1. General Tab 7.3.2. Extra Modes 7.3.3. Multipliers Tab 7.3.4. Preadder Tab 7.3.5. Accumulator Tab 7.3.6. Systolic/Chainout Tab 7.3.7. Pipelining Tab
8. ALTMULT_COMPLEX Intel® FPGA IP Core References x
8.1. ALTMULT_COMPLEX Intel FPGA IP Release Information 8.2. Features 8.3. Complex Multiplication 8.4. Parameters 8.5. Signals
9. LPM_MULT Intel® FPGA IP Core References x
9.1. LPM_MULT Intel FPGA IP Release Information 9.2. Features 9.3. Parameters 9.4. Signals
9.3. Parameters x
9.3.1. General Tab 9.3.2. General 2 Tab 9.3.3. Pipelining Tab
10. Native Floating Point DSP Stratix® 10 FPGA IP References x
10.1. Native Floating Point DSP Stratix® 10 FPGA IP Release Information 10.2. Native Floating Point DSP Stratix® 10 FPGA IP Core Supported Operational Modes 10.3. Parameterizing the Native Floating Point DSP Stratix® 10 FPGA IP 10.4. Native Floating Point DSP Stratix® 10 FPGA IP Core Signals
10.3. Parameterizing the Native Floating Point DSP Stratix® 10 FPGA IP x
10.3.1. Native Floating Point DSP Stratix® 10 FPGA IP Parameters
11. LPM_DIVIDE (Divider) Intel FPGA IP Core x
11.1. LPM_DIVIDE Intel® FPGA IP Release Information 11.2. Features 11.3. Verilog HDL Prototype 11.4. VHDL Component Declaration 11.5. VHDL LIBRARY_USE Declaration 11.6. Ports 11.7. Parameters
11.7. Parameters x
11.7.1. General Tab 11.7.2. General1 Tab
1. Stratix® 10 Variable Precision DSP Blocks Overview
2. Block Architecture Overview
3. Operational Mode Descriptions
4. Design Considerations
5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide
6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References
7. Multiply Adder IP Core References
8. ALTMULT_COMPLEX Intel® FPGA IP Core References
9. LPM_MULT Intel® FPGA IP Core References
10. Native Floating Point DSP Stratix® 10 FPGA IP References
11. LPM_DIVIDE (Divider) Intel FPGA IP Core
12. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives
13. Document Revision History for the Stratix® 10 Variable Precision DSP Blocks User Guide

6.4.1. Native Fixed Point DSP Stratix® 10 FPGA IP Parameters

Table 25.  General Parameters
Parameter IP Generated Parameter Value Default Value Description
Operation Mode
Select the Operation Mode operation_mode

m18×18_full

m18×18_full_top

m18×18_sumof2

m18×18_plus36

m18×18_systolic

m27×27

m18×18_full Select the desired operational mode.
Multiplier Configuration
Representation format for AX input bus signed_max

signed

unsigned

unsigned Specify the representation format for the top multiplier x operand.
Representation format for AY/AZ input buses signed_may

signed

unsigned

unsigned

Specify the representation format for the top multiplier y operand.

Representation format for BX input bus signed_mbx

signed

unsigned

unsigned Specify the representation format for the bottom multiplier x operand.
Representation format for BY/BZ input buses signed_mby

signed

unsigned

unsigned Specify the representation format for the bottom multiplier y operand.

Always select unsigned for m18×18_plus36 .

Clear Signal Setting
Type of clear signal clear_type

none

aclr

sclr

none

Select aclr to use asynchronous clear signal type for all registers.

Select sclr to use synchronous clear signal type for all registers.

Port Width Setting
How wide should AX input bus be? ax_width 1–27 18 Specify the width of ax input bus.

Refer to Maximum Input Data Width for Fixed-Point Arithmetic.

How wide should BX input bus be? bx_width 1–18 18 Specify the width of bx input bus.

Set this parameter to 0 when using m18x18_full_top mode.

Refer to Maximum Input Data Width for Fixed-Point Arithmetic.

How wide should AY input bus be? ay_scan_in_width 1–27 18 Specify the width of ay or scanin input bus.

Refer to Maximum Input Data Width for Fixed-Point Arithmetic.

How wide should BY input bus be? by_width 1–19 18 Specify the width of by input bus.

Set this parameter to 0 when using m18x18_full_top mode.

Refer to Maximum Input Data Width for Fixed-Point Arithmetic.

How wide should AZ input bus be? az_width 0-18 0 Specify the width of az input bus.

Refer to Maximum Input Data Width for Fixed-Point Arithmetic.

How wide should BZ input bus be? bz_width 0–18 0 Specify the width of bz input bus.

Set this parameter to 0 when using m18x18_full_top mode.

Refer to Maximum Input Data Width for Fixed-Point Arithmetic.

How wide should result A width? result_a_width 1–64 37 Specify the width of resulta output bus.
How wide should result B width? result_b_width 1–37 37 Specify the width of resultb output bus.

This parameter is supported only in m18x18_full mode.

How wide should result scanout port (1) scan_out_width 1–27 0 Specify the width of scanout output bus.
Figure 30. DSP Block ViewEach block is described in the DSP Block View Parameters table.
Table 26.  DSP Block View Parameters
Parameter Value Default Value Description
loadconst

Disable

Enable

 Disable

Click the port symbol to enable loadconst port and its input register.

accumulate port (2)

Disable

Enable

 Disable Click the port symbol to enable accumlate port and its input register.
negate port (3)

Disable

Enable

 Disable Click the port symbol to enable negate port and its input register.
sub port (4)

Disable

Enable

 Disable Click the port symbol to enable sub port and its input register.
Top delay register (5)

Disable

Enable

 Disable Click to enable the top delay register for ay input bus.

This feature is not supported in m18×18_plus36 and m27x27 operational mode.

Bottom delay register (6)

Disable

Enable

 Disable Click to enable bottom delay register for by input bus.

This feature is not supported in m18×18_plus36, m18x18_top_full, and m27x27 operational mode.

Scanout output bus (7)

Disable

Enable

 Disable Click to enable scanout output bus.
Input cascade for ay input (8)

Disable

Enable

 Disable

Click to enable input cascade module for ay input.

When you enable input cascade module, the Stratix 10 Native Fixed Point DSP IP core uses the scanin input signals as input instead of ay input signal.

Input cascade for by input (9)

Disable

Enable

 Disable

Click to enable input cascade module for by input.

When you enable input cascade module, the Stratix 10 Native Fixed Point DSP IP core uses the ay input signals as input instead of by input signal.

Register clock (10)

None

Clock 0

Clock 1

Clock 2

Clock 0

To bypass any register, switch the register clock to None.

Switch the register clock to:
  • Clock 0 to use clk[0] signal as the clock source
  • Clock 1 to use clk[1] signal as the clock source
  • Clock 2 to use clk[2] signal as the clock source
Top pre-adder (11)

Disable

Enable

 Disable

Click to enable top pre-adder module.

This uses az input bus as one of the operand source.

To use pre-adder feature, both top and bottom pre-adder modules must be enabled.

Top Pre-adder operation (12)

+

-

+ Click to switch the operation of top preadder between addition and subtraction.
Top coefficient module (13)

Disable

Enable

 Disable

Click to enable top internal coefficient module.

To use internal coefficient feature, both top and bottom internal coefficient modules must be enabled.

Bottom pre-adder (14)

Disable

Enable

 Disable

Click to enable bottom pre-adder module.

This uses bz input bus as one of the operand source.

To use pre-adder feature, both top and bottom pre-adder modules must be enabled.

Bottom coefficient module (15)

Disable

Enable

 Disable

Click to enable bottom internal coefficient module.

To use internal coefficient feature, both top and bottom internal coefficient modules must be enabled.

Bottom Pre-adder operation (16)

+

-

+ Click to switch the operation of bottom preadder between addition and subtraction.
Chainin input bus (17)

Disable

Enable

 Disable Click to enable Chainin input bus.
Clock enable for clock 0 (18)

Disable

Enable

 Disable Click to create clock enable signal for clock 0.
Clock enable for clock 1 (19)

Disable

Enable

 Disable Click to create clock enable signal for clock 1.
Clock enable for clock 2 (20)

Disable

Enable

 Disable Click to create clock enable signal for clock 2.
Clear signal for input registers (21)

Disable

Enable

 Disable Click to create Clr[0] signal for all input registers.

Use the Type of clear signal parameter to select asynchronous clear or synchronous clear for the input registers.

Clear signal for output and pipeline registers (22)

Disable

Enable

 Disable Click to create Clr[1] signal for all output and pipeline registers.

Use the Type of clear signal parameter to select asynchronous clear or synchronous clear for the output and pipeline registers.

Double accumulator module (23)

Disable

Enable

 Disable Click to enable double accumulator feature.
Chainout output bus (24)

Disable

Enable

 Disable Click to enable Chainout output bus.
Table 27.  Coefficient Configuration
Parameter IP Generated Parameter Value Default Value Description
Load Const Setting
What is the value for loadconst? load_const_value 0 - 63 0 Specify the preset constant value.

This value can be 2N where N is the preset constant value.

Coefficient A Storage Configuration
Coef_a_0 coef_a_0 Integer 0 Specify the coefficient values for ax input bus.

For 18-bit operation mode, the maximum input value is 218 - 1. For 27-bit operation, the maximum value is 227 - 1.

Coef_a_1 coef_a_1
Coef_a_2 coef_a_2
Coef_a_3 coef_a_3
Coef_a_4 coef_a_4
Coef_a_5 coef_a_5
Coef_a_6 coef_a_6
Coef_a_7 coef_a_7
Coefficient B Storage Configuration
Coef_b_0 coef_a_0 Integer 0 Specify the coefficient values for ax input bus.

Set coefficient values to more than 67108864 when operand is set to unsigned and negate is enabled.

Coef_b_1 coef_a_1
Coef_b_2 coef_a_2
Coef_b_3 coef_a_3
Coef_b_4 coef_a_4
Coef_b_5 coef_a_5
Coef_b_6 coef_a_6
Coef_b_7 coef_a_7
Related Information
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