Stratix® 10 Variable Precision DSP Blocks User Guide

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ID 683832
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Variable Precision DSP Blocks Overview 2. Block Architecture Overview 3. Operational Mode Descriptions 4. Design Considerations 5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide 6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References 7. Multiply Adder IP Core References 8. ALTMULT_COMPLEX Intel® FPGA IP Core References 9. LPM_MULT Intel® FPGA IP Core References 10. Native Floating Point DSP Stratix® 10 FPGA IP References 11. LPM_DIVIDE (Divider) Intel FPGA IP Core 12. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives 13. Document Revision History for the Stratix® 10 Variable Precision DSP Blocks User Guide
1. Stratix® 10 Variable Precision DSP Blocks Overview x
1.1. Features 1.2. Supported Operational Modes in Stratix® 10 Devices 1.3. Resources
2. Block Architecture Overview x
2.1. Input Register Bank for Fixed-Point and Floating-Point Arithmetic 2.2. Pipeline Registers for Fixed-Point and Floating-Point Arithmetic 2.3. Pre-adder for Fixed-Point Arithmetic 2.4. Internal Coefficient for Fixed-Point Arithmetic 2.5. Multipliers for Fixed-Point and Floating-Point Arithmetic 2.6. Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic 2.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic 2.8. Systolic Register for Fixed-Point Arithmetic 2.9. Double Accumulation Register for Fixed-Point Arithmetic 2.10. Output Register Bank for Fixed-Point and Floating-Point Arithmetic 2.11. Exception Handling for Floating-Point Arithmetic
3. Operational Mode Descriptions x
3.1. Operational Modes for Fixed-Point Arithmetic 3.2. Operational Modes for Floating-Point Arithmetic
3.1. Operational Modes for Fixed-Point Arithmetic x
3.1.1. Independent Multiplier Mode 3.1.2. Multiplier Adder Sum Mode 3.1.3. Independent Complex Multiplier 3.1.4. 18 × 19 Multiplication Summed with 36-Bit Input Mode 3.1.5. Systolic FIR Mode
3.1.1. Independent Multiplier Mode x
3.1.1.1. 18 × 18 or 18 × 19 Independent Multiplier 3.1.1.2. 27 × 27 Independent Multiplier
3.1.5. Systolic FIR Mode x
3.1.5.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.1.5.2. 18-bit Systolic FIR Mode 3.1.5.3. 27-Bit Systolic FIR Mode
3.2. Operational Modes for Floating-Point Arithmetic x
3.2.1. Single Floating-Point Arithmetic Functions 3.2.2. Multiple Floating-Point Arithmetic Functions
3.2.1. Single Floating-Point Arithmetic Functions x
3.2.1.1. Multiplication Mode 3.2.1.2. Adder or Subtract Mode 3.2.1.3. Multiply Accumulate Mode
3.2.2. Multiple Floating-Point Arithmetic Functions x
3.2.2.1. Multiply-Add or Multiply-Subtract Mode 3.2.2.2. Vector One Mode 3.2.2.3. Vector Two Mode 3.2.2.4. Direct Vector Dot Product 3.2.2.5. Complex Multiplication
4. Design Considerations x
4.1. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic 4.2. Accumulator for Fixed-Point Arithmetic 4.3. Chainout Adder 4.4. Input Cascade for Fixed-Point Arithmetic 4.5. DSP Block Cascade Limit in Agilex™ 7 Devices
5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide x
5.1. 'X' Propagation Support in Simulation
6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References x
6.1. Native Fixed Point DSP Stratix® 10 FPGA IP Release Information 6.2. Supported Operational Modes 6.3. Maximum Input Data Width for Fixed-Point Arithmetic 6.4. Parameterizing Native Fixed Point DSP IP Core 6.5. Signals
6.3. Maximum Input Data Width for Fixed-Point Arithmetic x
6.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example
6.4. Parameterizing Native Fixed Point DSP IP Core x
6.4.1. Native Fixed Point DSP Stratix® 10 FPGA IP Parameters
7. Multiply Adder IP Core References x
7.1. Multiply Adder Intel FPGA IP Release Information 7.2. Features 7.3. Parameters 7.4. Signals
7.2. Features x
7.2.1. Pre-adder 7.2.2. Systolic Delay Register 7.2.3. Pre-load Constant 7.2.4. Double Accumulator
7.2.1. Pre-adder x
7.2.1.1. Pre-adder Simple Mode 7.2.1.2. Pre-adder Coefficient Mode 7.2.1.3. Pre-adder Input Mode 7.2.1.4. Pre-adder Square Mode 7.2.1.5. Pre-adder Constant Mode
7.3. Parameters x
7.3.1. General Tab 7.3.2. Extra Modes 7.3.3. Multipliers Tab 7.3.4. Preadder Tab 7.3.5. Accumulator Tab 7.3.6. Systolic/Chainout Tab 7.3.7. Pipelining Tab
8. ALTMULT_COMPLEX Intel® FPGA IP Core References x
8.1. ALTMULT_COMPLEX Intel FPGA IP Release Information 8.2. Features 8.3. Complex Multiplication 8.4. Parameters 8.5. Signals
9. LPM_MULT Intel® FPGA IP Core References x
9.1. LPM_MULT Intel FPGA IP Release Information 9.2. Features 9.3. Parameters 9.4. Signals
9.3. Parameters x
9.3.1. General Tab 9.3.2. General 2 Tab 9.3.3. Pipelining Tab
10. Native Floating Point DSP Stratix® 10 FPGA IP References x
10.1. Native Floating Point DSP Stratix® 10 FPGA IP Release Information 10.2. Native Floating Point DSP Stratix® 10 FPGA IP Core Supported Operational Modes 10.3. Parameterizing the Native Floating Point DSP Stratix® 10 FPGA IP 10.4. Native Floating Point DSP Stratix® 10 FPGA IP Core Signals
10.3. Parameterizing the Native Floating Point DSP Stratix® 10 FPGA IP x
10.3.1. Native Floating Point DSP Stratix® 10 FPGA IP Parameters
11. LPM_DIVIDE (Divider) Intel FPGA IP Core x
11.1. LPM_DIVIDE Intel® FPGA IP Release Information 11.2. Features 11.3. Verilog HDL Prototype 11.4. VHDL Component Declaration 11.5. VHDL LIBRARY_USE Declaration 11.6. Ports 11.7. Parameters
11.7. Parameters x
11.7.1. General Tab 11.7.2. General1 Tab
1. Stratix® 10 Variable Precision DSP Blocks Overview
2. Block Architecture Overview
3. Operational Mode Descriptions
4. Design Considerations
5. Stratix® 10 Variable Precision DSP Blocks Implementation Guide
6. Native Fixed Point DSP Stratix® 10 FPGA IP Core References
7. Multiply Adder IP Core References
8. ALTMULT_COMPLEX Intel® FPGA IP Core References
9. LPM_MULT Intel® FPGA IP Core References
10. Native Floating Point DSP Stratix® 10 FPGA IP References
11. LPM_DIVIDE (Divider) Intel FPGA IP Core
12. Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives
13. Document Revision History for the Stratix® 10 Variable Precision DSP Blocks User Guide

7.4. Signals

The following tables list the input and output signals of the Multiply Adder Intel® FPGA IP core.

Table 43.   Multiply Adder Intel® FPGA IP Input Signals
Signal Required Description
dataa_0[]/dataa_1[]/dataa_2[]/dataa_3[] Yes Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_A - 1 … 0] wide

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals,the X value is propagated on the output signals.

datab_0[]/datab_1[]/datab_2[]/datab_3[] Yes Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_B - 1 … 0] wide

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

datac_0[] /datac_1[]/datac_2[]/datac_3[] No Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_C - 1, … 0] wide

Select INPUT for Select preadder mode parameter to enable these signals.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

clock[1:0] No Clock input port to the corresponding register. This signal can be used by any register in the IP core.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

aclr[1:0] No Asynchronous clear input to the corresponding register.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

sclr[1:0] No Synchronous clear input to the corresponding register.

The simulation model for this IP supports undetermined input value X to these signals. When you provide X value to these signals, the X value is propagated on the output signals

ena[1:0] No Enable signal input to the corresponding register.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

signa No Specifies the numerical representation of the multiplier input A. If the signa signal is high, the multiplier treats the multiplier input A signal as a signed number. If the signa signal is low, the multiplier treats the multiplier input A signal as an unsigned number.

Select VARIABLE for What is the representation format for Multipliers A inputs parameter to enable this signal.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

signb No Specifies the numerical representation of the multiplier input B signal. If the signb signal is high, the multiplier treats the multiplier input B signal as a signed two's complement number. If the signb signal is low, the multiplier treats the multiplier input B signal as an unsigned number.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

scanina[] No Input for scan chain A. Input signal [WIDTH_A - 1, ... 0] wide. When the INPUT_SOURCE_A parameter has a value of SCANA, the scanina[] signal is required.
accum_sload No Dynamically specifies whether the accumulator value is constant. If the accum_sload signal is low, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

sload_accum No Dynamically specifies whether the accumulator value is constant. If the sload_accum signal is high, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

chainin[] No Adder result input bus from the preceding stage. Input signal [WIDTH_CHAININ - 1, … 0] wide.
addnsub1 No Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub1 signal to add the outputs from the first pair of multipliers. Input 0 to addnsub1 signal to subtract the outputs from the first pair of multipliers.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

addnsub3 No Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub3 signal to add the outputs from the second pair of multipliers. Input 0 to addnsub3 signal to subtract the outputs from the first pair of multipliers.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel0[] No Coefficient input signal[0:3] to the first multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel1[] No Coefficient input signal[0:3]to the second multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel2[] No Coefficient input signal[0:3]to the third multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel3[] No Coefficient input signal [0:3] to the fourth multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

Table 44.   Multiply Adder Intel® FPGA IP Output Signals
Signal Required Description
result [] Yes Multiplier output signal. Output signal [WIDTH_RESULT - 1 … 0] wide

The simulation model for this IP supports undetermined output value (X). When you provide X value as the input, the X value is propagated on this signal.

scanouta [] No Output of scan chain A. Output signal [WIDTH_A - 1..0] wide.

Select more than 2 for numbers of multipliers and choose Scan chain input for What is the input A of the multiplier connected to parameter to enable this signal.

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