Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

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ID 683832
Date 8/13/2021
Public
Document Table of Contents
Document Table of Contents
1. Intel® Stratix® 10 Variable Precision DSP Blocks Overview 2. Block Architecture Overview 3. Operational Mode Descriptions 4. Design Considerations 5. Intel® Stratix® 10 Variable Precision DSP Blocks Implementation Guide 6. Native Fixed Point DSP Intel® Stratix® 10 FPGA IP Core References 7. Multiply Adder IP Core References 8. ALTMULT_COMPLEX Intel® FPGA IP Core Reference 9. LPM_MULT Intel® FPGA IP Core References 10. Native Floating Point DSP Intel® Stratix® 10 FPGA IP References 11. LPM_DIVIDE (Divider) Intel FPGA IP Core 12. Intel® Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives 13. Document Revision History for the Intel® Stratix® 10 Variable Precision DSP Blocks User Guide
1. Intel® Stratix® 10 Variable Precision DSP Blocks Overview
1.1. Features 1.2. Supported Operational Modes in Intel® Stratix® 10 Devices 1.3. Resources
2. Block Architecture Overview
2.1. Input Register Bank for Fixed-Point and Floating-Point Arithmetic 2.2. Pipeline Registers for Fixed-Point and Floating-Point Arithmetic 2.3. Pre-adder for Fixed-Point Arithmetic 2.4. Internal Coefficient for Fixed-Point Arithmetic 2.5. Multipliers for Fixed-Point and Floating-Point Arithmetic 2.6. Adder or Subtractor for Fixed-Point and Floating-Point Arithmetic 2.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-Point Arithmetic 2.8. Systolic Register for Fixed-Point Arithmetic 2.9. Double Accumulation Register for Fixed-Point Arithmetic 2.10. Output Register Bank for Fixed-Point and Floating-Point Arithmetic 2.11. Exception Handling for Floating-Point Arithmetic
3. Operational Mode Descriptions
3.1. Operational Modes for Fixed-Point Arithmetic 3.2. Operational Modes for Floating-Point Arithmetic
3.1. Operational Modes for Fixed-Point Arithmetic
3.1.1. Independent Multiplier Mode 3.1.2. Multiplier Adder Sum Mode 3.1.3. Independent Complex Multiplier 3.1.4. 18 × 19 Multiplication Summed with 36-Bit Input Mode 3.1.5. Systolic FIR Mode
3.1.1. Independent Multiplier Mode
3.1.1.1. 18 × 18 or 18 × 19 Independent Multiplier 3.1.1.2. 27 × 27 Independent Multiplier
3.1.5. Systolic FIR Mode
3.1.5.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.1.5.2. 18-bit Systolic FIR Mode 3.1.5.3. 27-Bit Systolic FIR Mode
3.2. Operational Modes for Floating-Point Arithmetic
3.2.1. Single Floating-Point Arithmetic Functions 3.2.2. Multiple Floating-Point Arithmetic Functions
3.2.1. Single Floating-Point Arithmetic Functions
3.2.1.1. Multiplication Mode 3.2.1.2. Adder or Subtract Mode 3.2.1.3. Multiply Accumulate Mode
3.2.2. Multiple Floating-Point Arithmetic Functions
3.2.2.1. Multiply-Add or Multiply-Subtract Mode 3.2.2.2. Vector One Mode 3.2.2.3. Vector Two Mode 3.2.2.4. Direct Vector Dot Product 3.2.2.5. Complex Multiplication
4. Design Considerations
4.1. Internal Coefficient and Pre-Adder for Fixed-Point Arithmetic 4.2. Accumulator for Fixed-Point Arithmetic 4.3. Chainout Adder 4.4. Input Cascade for Fixed-Point Arithmetic 4.5. DSP Block Cascade Limit in Intel® Stratix® 10 Devices
5. Intel® Stratix® 10 Variable Precision DSP Blocks Implementation Guide
5.1. 'X' Propagation Support in Simulation
6. Native Fixed Point DSP Intel® Stratix® 10 FPGA IP Core References
6.1. Native Fixed Point DSP Intel® Stratix® 10 FPGA IP Release Information 6.2. Supported Operational Modes 6.3. Maximum Input Data Width for Fixed-Point Arithmetic 6.4. Parameterizing Native Fixed Point DSP IP Core 6.5. Signals
6.3. Maximum Input Data Width for Fixed-Point Arithmetic
6.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example
6.4. Parameterizing Native Fixed Point DSP IP Core
6.4.1. Native Fixed Point DSP Intel® Stratix® 10 FPGA IP Parameters
7. Multiply Adder IP Core References
7.1. Multiply Adder Intel FPGA IP Release Information 7.2. Features 7.3. Parameters 7.4. Signals
7.2. Features
7.2.1. Pre-adder 7.2.2. Systolic Delay Register 7.2.3. Pre-load Constant 7.2.4. Double Accumulator
7.2.1. Pre-adder
7.2.1.1. Pre-adder Simple Mode 7.2.1.2. Pre-adder Coefficient Mode 7.2.1.3. Pre-adder Input Mode 7.2.1.4. Pre-adder Square Mode 7.2.1.5. Pre-adder Constant Mode
7.3. Parameters
7.3.1. General Tab 7.3.2. Extra Modes 7.3.3. Multipliers Tab 7.3.4. Preadder Tab 7.3.5. Accumulator Tab 7.3.6. Systolic/Chainout Tab 7.3.7. Pipelining Tab
8. ALTMULT_COMPLEX Intel® FPGA IP Core Reference
8.1. ALTMULT_COMPLEX Intel FPGA IP Release Information 8.2. Features 8.3. Complex Multiplication 8.4. Parameters 8.5. Signals
9. LPM_MULT Intel® FPGA IP Core References
9.1. LPM_MULT Intel FPGA IP Release Information 9.2. Features 9.3. Parameters 9.4. Signals
9.3. Parameters
9.3.1. General Tab 9.3.2. General 2 Tab 9.3.3. Pipelining Tab
10. Native Floating Point DSP Intel® Stratix® 10 FPGA IP References
10.1. Native Floating Point DSP Intel® Stratix® 10 FPGA IP Release Information 10.2. Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core Supported Operational Modes 10.3. Parameterizing the Native Floating Point DSP Intel® Stratix® 10 FPGA IP 10.4. Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core Signals
10.3. Parameterizing the Native Floating Point DSP Intel® Stratix® 10 FPGA IP
10.3.1. Native Floating Point DSP Intel® Stratix® 10 FPGA IP Parameters
11. LPM_DIVIDE (Divider) Intel FPGA IP Core
11.1. LPM_DIVIDE Intel® FPGA IP Release Information 11.2. Features 11.3. Verilog HDL Prototype 11.4. VHDL Component Declaration 11.5. VHDL LIBRARY_USE Declaration 11.6. Ports 11.7. Parameters
11.7. Parameters
11.7.1. General Tab 11.7.2. General1 Tab
1. Intel® Stratix® 10 Variable Precision DSP Blocks Overview
2. Block Architecture Overview
3. Operational Mode Descriptions
4. Design Considerations
5. Intel® Stratix® 10 Variable Precision DSP Blocks Implementation Guide
6. Native Fixed Point DSP Intel® Stratix® 10 FPGA IP Core References
7. Multiply Adder IP Core References
8. ALTMULT_COMPLEX Intel® FPGA IP Core Reference
9. LPM_MULT Intel® FPGA IP Core References
10. Native Floating Point DSP Intel® Stratix® 10 FPGA IP References
11. LPM_DIVIDE (Divider) Intel FPGA IP Core
12. Intel® Stratix® 10 Variable Precision DSP Blocks User Guide Document Archives
13. Document Revision History for the Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

2.2. Pipeline Registers for Fixed-Point and Floating-Point Arithmetic

In addition to the input and output registers, there are 2 columns of pipeline registers for fixed-point arithmetic. Pipeline registers are used to get the maximum Fmax performance. The pipeline registers can be bypassed if high Fmax is not needed.

The following variable precision DSP block signals control the pipeline registers within the variable precision DSP block:
  • CLK[2..0]
  • ENA[2..0]
  • CLR[1]

Floating-point arithmetic has 3 latency layers of pipeline registers. You can bypass all latency layers of the pipeline registers or use any one, two or three layers of pipeline registers.

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