7. Multiply Adder IP Core References
The Multiply Adder Intel® FPGA IP core allows you to implement a multiplier-adder.9
The following figure shows the ports for the Multiply Adder Intel® FPGA IP core.
A multiplier-adder accepts pairs of inputs, multiplies the values together and then adds to or subtracts from the products of all other pairs.
The DSP block uses 18 × 19-bit input multipliers to process data with widths up to 18 bits and 27 × 27 bit input multipliers to process data with widths between 18 to 27 bits. For data with widths more than 27 bits, the DSP block uses partial products algorithm to process the data and 27 × 27-bit input multiplier to process data with widths between 18 to 27 bits.
The registers and extra pipeline registers for the following signals are also placed inside the DSP block:
- Data input
- Signed or unsigned select
- Add or subtract select
- Products of multipliers
In the case of the output result, the first register is placed in the DSP block. However the extra latency registers are placed in logic elements outside the block. Peripheral to the DSP block, including data inputs to the multiplier, control signal inputs, and outputs of the adder, use regular routing to communicate with the rest of the device. All connections in the function use dedicated routing inside the DSP block. This dedicated routing includes the shift register chains when you select the option to shift a multiplier's registered input data from one multiplier to an adjacent multiplier.
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