Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

5.1. 'X' Propagation Support in Simulation

The following Intel® Stratix® 10 variable precision DSP IPs support undetermined value (X) for input signals in simulation starting from Intel® Quartus® Prime Pro Edition v20.3:
  • Native Fixed Point DSP Intel® Stratix® 10 FPGA IP
  • Multiply Adder IP
  • ALTMULT_COMPLEX Intel® FPGA IP
  • LPM_MULT Intel® FPGA IP
  • Native Floating Point DSP Intel® Stratix® 10 FPGA IP
When you drive any input signals with the value of X, the output of the DSP block results to an X value because the arithmetic operation is unable to perform with an undetermined value. This feature is supported for both fixed-point and floating-point arithmetic.

To enable this feature, you must include the define flag option "ENA_INPUT_X_PROP" in the simulation command before compiling the variable precision DSP IP simulation models.

The following is an example of adding the define flag into the simulation command:
vlog -sv -timescale 1ps/1ps +define+ENA_INPUT_X_PROP -work msim_precompile $env(QUARTUS_DIR)/eda/sim_lib/altera_lnsim.sv

The following table shows the supported input and output values of the DSP block simulation model.

Table 19.  Supported Input and Output Values for Fixed-point Arithmetic
Inputs (ax/ay/az/bx/by/bz/coefsela/coefselb signals) Dynamic Control Inputs (ACCUMULATE/LOADCONST/SUB/NEGATE signals) Outputs (resulta/resultb signals)
Not X value Not X value Not X value
X value Not X value X value
Not X value X value X value
X value X value X value
Table 20.  Supported Input and Output Values for Floating-point Arithmetic
Inputs (ax/ay/az signals) Dynamic Control Inputs (ACCUMULATE signal) Outputs (resulta/mult_overflow/mult_inexact/ mult_invalid/adder_overflow/adder_underflow/ adder_inexact/adder_invalid signals)
Not X value Not X value Not X value
X value Not X value X value
Not X value X value X value
X value X value X value
Table 21.  Supported Input and Output Values for Clock, Clear and Clock Enable Inputs
Inputs (clk/clr/ena signals) Outputs (resulta/resultb signals)
Not X value Not X value
X value X value

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