Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

10.4. Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core Signals

Figure 47.  Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core Signals

The figure shows the input and output signals of the Native Floating Point DSP Intel® Stratix® 10 FPGA IP core.

Table 58.   Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core Signals
Signal Name Type Width Default Description
ax[31:0] Input 32 Low Input data bus to the multiplier.
Available in:
  • Add mode
  • Multiply-Add mode without chainin and chainout feature
  • Vector Mode 1
  • Vector Mode 2

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

ay[31:0] Input 32 Low Input data bus to the multiplier.

Available in all floating-point operational modes.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

az[31:0] Input 32 Low

Input data bus to the multiplier.

Available in:
  • Multiply
  • Multiply Add
  • Multiply Accumulate
  • Vector Mode 1
  • Vector Mode 2

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

chainin[31:0] Input 32 Low

Connect these signals to the chainout signals from the preceding floating-point DSP IP core.

clk[2:0] Input 3 Low Input clock signals for all registers.

These clock signals are only available if any of the input registers, pipeline registers, or output register is set to Clock0 or Clock1 or Clock2.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

ena[2:0] Input 3 High Clock enable for clk[2:0].

These signals are active-High.

  • ena[0] is for Clock0
  • ena[1] is for Clock1
  • ena[2] is for Clock2

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

clr[1:0] Input 2 Low

These signals are active-high.

Use clr[0] for all input registers and use clr[1] for all pipeline and output registers.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

accumulate Input 1 Low Input signal to enable or disable the accumulator feature.
  • Assert this signal to enable feedback the adder's output.
  • De-assert this signal to disable the feedback mechanism.

You can assert or de-assert this signal during run-time.

Available in Multiply Accumulate mode.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this signal, the X value is propagated on the output signals.

chainout[31:0] Output 32 Connect these signals to the chainin signals of the next floating-point DSP IP core.
result[31:0] Output 32 Output data bus from IP core.

The simulation model for this IP supports undetermined output value (X). When you provide X value as the input, the X value is propagated on this signal.

mult_overflow Output 1  

This signal indicates if the multiplier result is a larger value compared to the maximum presentable value.

1: If the multiplier result is a larger value compared to the maximum representable value and the result is cast to infinity.

0: If the multiplier result is not larger than the maximum presentable value.

Not available in Adder mode.

mult_underflow Output 1

This signal indicates if the multiplier result is a smaller value compared to the minimum presentable value.

1: If the multiplier result is a smaller value compared to the minimum representable value and the result is flushed to zero.

0: If the multiplier result is a larger than the minimum representable value.

Not available in Adder mode.

mult_inexact Output 1

This signal indicates if the multiplier result is an exact representation.

1: If the multiplier result is:
  • a rounded value or
  • a smaller value compared to the minimum representable value or
  • a larger value compared to the maximum representable value.

0: If the multiplier result does not meet any of the criteria above.

Not available in Adder mode.

mult_invalid Output 1

This signal indicates if the multiplier operation is ill-defined and produces an invalid result.

1: If the multiplier result is invalid and cast to qNaN.

0: If the multiplier result is not an invalid number.

Not available in Adder mode.

adder_overflow Output 1

This signal indicates if the adder result is a larger value compared to the maximum representable value.

1: If the adder result is a larger value compared to the maximum presentable value and the result is cast to infinity.

0: If the multiplier result is not larger than the maximum presentable value.

Not available in Multiply mode.

adder_underflow Output 1

This signal indicates if the adder result is a smaller value compared to the minimum presentable value.

1: If the multiplier result is a smaller value compared to the minimum representable value and the result is flushed to zero.

0: If the multiplier result is a larger than the minimum representable value.

Not available in Multiply mode.

adder_inexact Output 1

This signal indicates if the adder result is an exact representation.

1: If the adder result is:
  • a rounded value
  • a smaller value compared to the minimum representable value or
  • a larger value compared to the maximum representable value.

0: If the multiplier result does not meet any of the criteria above.

Not available in Multiply mode.

adder_invalid Output 1

This signal indicates if the adder operation is ill-defined and produces an invalid result.

1: If the multiplier result is invalid and cast to qNaN.

0: If the multiplier result is not an invalid number.

Not available in Multiply mode.

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