Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

7.3.3. Multipliers Tab

Table 38.  Multipliers Tab
Parameter Value Default Value Description
What is the representation format for Multipliers A inputs?

SIGNED,

UNSIGNED,

VARIABLE

UNSIGNED Specify the representation format for the multiplier A input.
Register ‘signa’ input

On

Off

Off Select this option to enable signa register.

You must select VARIABLE value for What is the representation format for Multipliers A inputs? parameter to enable this option.

What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to enable and specify the input clock signal for signa register.

You must select Register ‘signa’ input to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the signa register.

You must select Register ‘signa’ input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the signa register.

You must select Register ‘signa’ input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the representation format for Multipliers B inputs?

SIGNED,

UNSIGNED,

VARIABLE

UNSIGNED Specify the representation format for the multiplier B input.
Register ‘signb’ input

On

Off

Off Turn on this option to enable signb register.

You must select VARIABLE value for What is the representation format for Multipliers B inputs? parameter to enable this option.

What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to enable and specify the input clock signal for signb register.

You must select Register ‘signb’ input to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the asynchronous clear source for the signb register.

You must select Register ‘signb’ input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the synchronous clear source for the signb register.

You must select Register ‘signb’ input to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

Input Configuration
Register input A of the multiplier

On

Off

Off Turn on this option to enable input register for dataa input bus.
What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to enable and specify the register input clock signal for dataa input bus.

You must select Register input A of the multiplier to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the register asynchronous clear source for the dataa input bus.

You must select Register input A of the multiplier to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the register synchronous clear source for the dataa input bus.

You must select Register input A of the multiplier to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

Register input B of the multiplier

On

Off

Off Turn on this option to enable input register for datab input bus.
What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to enable and specify the register input clock signal for datab input bus.

You must select Register input B of the multiplier to enable this parameter.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the register asynchronous clear source for the datab input bus.

You must select Register input B of the multiplier to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the register synchronous clear source for the datab input bus.

You must select Register input B of the multiplier to enable this parameter.

The IP core supports either asynchronous or synchronous clear but not both.

What is the input A of the multiplier connected to?

Multiplier input

Scan chain input

Multiplier input Select the input source for input A of the multiplier.

Select Multiplier input to use dataa input bus as the source to the multiplier.

Select Scan chain input to use scanin input bus as the source to the multiplier and enable the scanout output bus.

This parameter is available when you select 2, 3 or 4 for What is the number of multipliers? parameter.

Scanout A Register Configuration
Register output of the scan chain

On

Off

Off Turn on this option to enable output register for scanouta output bus.

You must select Scan chain input for What is the input A of the multiplier connected to? parameter to enable this option.

What is the source for clock input?

Clock0

Clock1

Clock2

Clock0 Select Clock0 , Clock1 or Clock2 to enable and specify the register input clock signal for scanouta output bus.

You must turn on Register output of the scan chain parameter to enable this option.

What is the source for asynchronous clear input?

NONE

ACLR0

ACLR1

NONE Specifies the register asynchronous clear source for the scanouta output bus.

You must turn on Register output of the scan chain parameter to enable this option.

The IP core supports either asynchronous or synchronous clear but not both.

What is the source for synchronous clear input?

NONE

SCLR0

SCLR1

NONE Specifies the register synchronous clear source for the scanouta output bus.

You must select Register output of the scan chain parameter to enable this option.

The IP core supports either asynchronous or synchronous clear but not both.

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