ID 683832
Date 8/13/2021
Public

## 10.2. Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core Supported Operational Modes

Table 56.  Operational Modes Supported by Native Floating Point DSP Intel® Stratix® 10 FPGA IP Core
Operational Modes Description Supported Exception Flags
Multiply mode

This mode performs single precision multiplication operation.

This mode applies the following equation:
• Out = Ay * Az
• mult_overflow
• mult_underflow
• mult_inexact
• mult_invalid
This mode applies the following equations:
• Out = Ay + Ax
• Out = Ay - Ax

This mode performs single precision multiplication, followed by addition or subtraction operations.

This mode applies the following equations:
• Out = (Ay * Az) - chainin
• Out = (Ay * Az) + chainin
• Out = (Ay * Az) - Ax
• Out = (Ay * Az) + Ax
• mult_overflow
• mult_underflow
• mult_inexact
• mult_invalid
Multiply Accumulate mode

This mode performs floating-point multiplication followed by floating-point addition or subtraction with the previous multiplication result.

This mode applies the following equations:
• Out(t) = [Ay(t) * Az(t)] - Out (t-1) when accumulate signal is driven high.
• Out(t) = [Ay(t) * Az(t)] + Out (t-1) when accumulate port is driven high.
• Out(t) = Ay(t) * Az(t) when accumulate port is driven low.
Vector Mode 1

This mode performs floating-point multiplication followed by floating-point addition or subtraction with the chainin input from the previous variable DSP Block.

This mode applies the following equations:
• Out = (Ay * Az) - chainin, chainout = Ax
• Out = (Ay * Az) + chainin , chainout = Ax
• Out = (Ay * Az) , chainout = Ax
Vector Mode 2 This mode performs floating-point multiplication where the multiplication result is directly fed to chainout. The chainin input from the previous variable DSP Block is then added or subtracted from input Ax as the output result.

This mode applies the following equations:

• Out = Ax - chainin , chainout = Ay * Az
• Out = Ax + chainin , chainout = Ay * Az
• Out = Ax , chainout = Ay * Az