Intel® Stratix® 10 Variable Precision DSP Blocks User Guide

ID 683832
Date 8/13/2021
Public
Document Table of Contents

8.4. Parameters

Table 46.   ALTMULT_COMPLEX Intel® FPGA IP Parameters
Parameter Value Default Value Description
General
How wide should the A input buses be? 1–256 18 Specifies the number of bits for dataa_imag and dataa_real input buses.
How wide should the B input buses be? 1–256 18 Specifies the number of bits for datab_imag and datab_real input buses.
How wide should the ‘result’ output bus be? 1–256 36 Specifies the number of bits for ‘result’ output bus.
Input Representation
What is the representation format for A inputs?

Signed,

Unsigned

Signed Specifies the representation format for A inputs.

Only Signed representation format is supported in Intel® Stratix® 10 devices.

What is the representation format for B inputs?

Signed,

Unsigned

Signed Specifies the representation format for B inputs.

Only Signed representation format is supported in Intel® Stratix® 10 devices.

Implementation Style
Which implementation style should be used?

Automatically select a style for best trade-off for the current settings

Canonical. (Minimize the number of simple multipliers)

Conventional. (Minimize the use of logic cells)

Automatically select a style for best trade-off for the current settings Intel® Stratix® 10 devices supports only Automatically select a style for best trade-off for the current settings style. The Intel® Quartus® Prime software determines the best implementation based on the selected device family and input width.
Pipelining
Output latency 0 - 11 4 Specifies the number of clock cycles for output latency.
Create a Clear input?

NONE

ACLR

SCLR

NONE Select this option to create aclr or sclr signal for the complex multiplier.
Create a Clock Enable input?

On

Off

Off Select this option to create ena signal for the complex multiplier clock.

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