Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 10/31/2022
Document Table of Contents

Memory Output Clock Jitter Specifications

Intel® MAX® 10 devices support external memory interfaces up to 303 MHz. The external memory interfaces for Intel® MAX® 10 devices calibrate automatically.

The memory output clock jitter measurements are for 200 consecutive clock cycles.

The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a PHY clock network.

DDR3 and LPDDR2 SDRAM memory interfaces are only supported on the fast speed grade device.

Table 50.  Memory Output Clock Jitter Specifications for Intel® MAX® 10 Devices
Parameter Symbol –6 Speed Grade –7 Speed Grade Unit
Min Max Min Max
Clock period jitter tJIT(per) –127 127 –215 215 ps
Cycle-to-cycle period jitter tJIT(cc) 242 360 ps

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