Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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Differential SSTL I/O Standards Specifications

Differential SSTL requires a VREF input.

Table 23.  Differential SSTL I/O Standards Specifications for Intel® MAX® 10 Devices
I/O Standard VCCIO (V) VSwing(DC) (V) VX(AC) (V) VSwing(AC) (V)
Min Typ Max Min Max18 Min Typ Max Min Max
SSTL-2 Class I, II 2.375 2.5 2.625 0.36 VCCIO VCCIO/2 – 0.2 VCCIO/2+ 0.2 0.7 VCCIO
SSTL-18 Class I, II 1.7 1.8 1.9 0.25 VCCIO VCCIO/2 – 0.175 VCCIO/2+ 0.175 0.5 VCCIO
SSTL-15 Class I, II 1.425 1.5 1.575 0.2 VCCIO/2 – 0.15 VCCIO/2 + 0.15 2(VIH(AC) – VREF) 2(VIL(AC) – VREF)
SSTL-135 1.283 1.35 1.45 0.18 VREF – 0.135 0.5 × VCCIO VREF + 0.135 2(VIH(AC) – VREF) 2(VIL(AC) – VREF)
18 The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC) and VIL(DC)).