Intel® MAX® 10 FPGA Device Datasheet

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ID 683794
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® MAX® 10 FPGA Device Datasheet
Intel® MAX® 10 FPGA Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® MAX® 10 FPGA Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame Recommended Operating Conditions Programming/Erasure Specifications DC Characteristics I/O Standards Specifications
Absolute Maximum Ratings x
Single Supply Devices Absolute Maximum Ratings Dual Supply Devices Absolute Maximum Ratings Absolute Maximum Ratings
Recommended Operating Conditions x
Single Supply Devices Power Supplies Recommended Operating Conditions Dual Supply Devices Power Supplies Recommended Operating Conditions Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Parameters Series OCT without Calibration Specifications Series OCT with Calibration at Device Power-Up Specifications OCT Variation after Calibration at Device Power-Up Pin Capacitance Internal Weak Pull-Up Resistor Hot-Socketing Specifications Hysteresis Specifications for Schmitt Trigger Input
I/O Standards Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Performance Specifications Internal Oscillator Specifications UFM Performance Specifications ADC Performance Specifications
ADC Performance Specifications x
Single Supply Devices ADC Performance Specifications Dual Supply Devices ADC Performance Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications Memory Standards Supported by the Soft Memory Controller Memory Output Clock Jitter Specifications
High-Speed I/O Specifications x
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications True LVDS Transmitter Timing Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Remote System Upgrade Circuitry Timing Specifications User Watchdog Internal Circuitry Timing Specifications Uncompressed Raw Binary File (.rbf) Sizes Internal Configuration Time Internal Configuration Timing Parameter
Programmable IOE Delay x
Programmable IOE Delay On Row Pins Programmable IOE Delay for Column Pins
Intel® MAX® 10 FPGA Device Datasheet

Single Supply Devices ADC Performance Specifications

Table 34.  ADC Performance Specifications for Intel® MAX® 10 Single Supply Devices
Parameter Symbol Condition Min Typ Max Unit
ADC resolution — — — — 12 bits
ADC supply voltage VCC_ONE — 2.85 3.0/3.3 3.465 V
External reference voltage VREF — VCC_ONE – 0.5 — VCC_ONE V
Sampling rate FS Accumulative sampling rate — — 1 MSPS
Operating junction temperature range TJ — –40 25 125 °C
Analog input voltage VIN Prescalar disabled 0 — VREF V
Prescalar enabled 37 0 — 3.6 V
Input resistance RIN — — 38 — —
Input capacitance CIN — — 38 — —
DC Accuracy Offset error and drift Eoffset Prescalar disabled –0.2 — 0.2 %FS
Prescalar enabled –0.5 — 0.5 %FS
Gain error and drift Egain Prescalar disabled –0.5 — 0.5 %FS
Prescalar enabled –0.75 — 0.75 %FS
Differential non linearity DNL External VREF, no missing code –0.9 — 0.9 LSB
Internal VREF, no missing code –1 — 1.7 LSB
Integral non linearity INL — –2 — 2 LSB
AC Accuracy Total harmonic distortion THD FIN = 50 kHz, FS = 1 MHz, PLL –65 39 — — dB
Signal-to-noise ratio SNR FIN = 50 kHz, FS = 1 MHz, PLL 54 40 — — dB
Signal-to-noise and distortion SINAD FIN = 50 kHz, FS = 1 MHz, PLL 53 41 — — dB
On-Chip Temperature Sensor Temperature sampling rate TS — — — 50 kSPS
Absolute accuracy — –40 to 125°C,

with 64 samples averaging

42 		— — ±10 °C
Conversion Rate 43 Conversion time — Single measurement — — 1 Cycle
Continuous measurement — — 1 Cycle
Temperature measurement — — 1 Cycle
Related Information
37 Prescalar function divides the analog input voltage by half. The analog input handles up to 3.6 V for the Intel® MAX® 10 single supply devices.
38 Download the SPICE models for simulation.
39 THD with prescalar enabled is 6dB less than the specification.
40 SNR with prescalar enabled is 6dB less than the specification.
41 SINAD with prescalar enabled is 6dB less than the specification.
42 For the Intel® Quartus® Prime software version 15.0 and later, Modular ADC Core Intel® FPGA IP and Modular Dual ADC Core Intel® FPGA IP cores handle the 64 samples averaging. For the Intel® Quartus® Prime software versions prior to 14.1, you need to implement your own averaging calculation.
43 For more detailed description, refer to the Timing section in the Intel® MAX® 10 Analog-to-Digital Converter User Guide.
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