Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
Public
Download
Document Table of Contents

Glossary

Table 59.  Glossary
Term Definition
JTAG Timing Specifications
RL Receiver differential input discrete resistor (external to Intel® MAX® 10 devices).
RSKM (Receiver input skew margin) HIGH-SPEED I/O block: The total margin left after accounting for the sampling window and TCCS. RSKM = (TUI – SW – TCCS) / 2.
Sampling window (SW) HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Single-ended voltage referenced I/O standard

The AC input signal values indicate the voltage levels at which the receiver must meet its timing specifications. The DC input signal values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver changes to the new logic state.

The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing.

tC High-speed receiver/transmitter input and output clock period.
TCCS (Channel-to- channel-skew) HIGH-SPEED I/O block: The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement.
tcin Delay from clock pad to I/O input register.
tCO Delay from clock pad to I/O output.
tcout Delay from clock pad to I/O output register.
tDUTY HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
tFALL Signal high-to-low transition time (80–20%).
tH Input register hold time.
Timing Unit Interval (TUI) HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER Period jitter on PLL clock input.
tOUTJITTER_DEDCLK Period jitter on dedicated clock output driven by a PLL.
tOUTJITTER_IO Period jitter on general purpose I/O driven by a PLL.
tpllcin Delay from PLL inclk pad to I/O input register.
tpllcout Delay from PLL inclk pad to I/O output register.
tRISE Signal low-to-high transition time (20–80%).
tSU Input register setup time.
VCM(DC) DC common mode input voltage.
VDIF(AC) AC differential input voltage: The minimum AC input differential voltage required for switching.
VDIF(DC) DC differential input voltage: The minimum DC input differential voltage required for switching.
VHYS Hysteresis for Schmitt trigger input.
VICM Input common mode voltage: The common mode of the differential signal at the receiver.
VID Input differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver.
VIH Voltage input high: The minimum positive voltage applied to the input which is accepted by the device as a logic high.
VIH(AC) High-level AC input voltage.
VIH(DC) High-level DC input voltage.
VIL Voltage input low: The maximum positive voltage applied to the input which is accepted by the device as a logic low.
VIL (AC) Low-level AC input voltage.
VIL (DC) Low-level DC input voltage.
VIN DC input voltage.
VOCM Output common mode voltage: The common mode of the differential signal at the transmitter.
VOD Output differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. VOD = VOH – VOL.
VOH Voltage output high: The maximum positive voltage from an output which the device considers is accepted as the minimum positive high level.
VOL Voltage output low: The maximum positive voltage from an output which the device considers is accepted as the maximum positive low level.
VOS Output offset voltage: VOS = (VOH + VOL) / 2.
VOX (AC) AC differential Output cross point voltage: The voltage at which the differential output signals must cross.
VREF Reference voltage for SSTL, HSTL, and HSUL I/O Standards.
VREF(AC) AC input reference voltage for SSTL, HSTL, and HSUL I/O Standards. VREF(AC) = VREF(DC) + noise. The peak-to-peak AC noise on VREF should not exceed 2% of VREF(DC).
VREF(DC) DC input reference voltage for SSTL, HSTL, and HSUL I/O Standards.
VSWING (AC) AC differential input voltage: AC Input differential voltage required for switching.
VSWING (DC) DC differential input voltage: DC Input differential voltage required for switching.
VTT Termination voltage for SSTL, HSTL, and HSUL I/O Standards.
VX (AC) AC differential Input cross point voltage: The voltage at which the differential input signals must cross.

Did you find the information on this page useful?

Characters remaining:

Feedback Message