Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Parameters Series OCT without Calibration Specifications Series OCT with Calibration at Device Power-Up Specifications OCT Variation after Calibration at Device Power-Up Pin Capacitance Internal Weak Pull-Up Resistor Hot-Socketing Specifications Hysteresis Specifications for Schmitt Trigger Input
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications True LVDS Transmitter Timing Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.
For example, a signal that overshoots to 4.17 V can only be at 4.17 V for ~11.7% over the lifetime of the device; for a device lifetime of 11.4 years, this amounts to 1.33 years.
|Condition (V)||Overshoot Duration as % of High Time||Unit|
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