Visible to Intel only — GUID: mcn1397819620952
Ixiasoft
Supply Current and Power Consumption
I/O Pin Leakage Current
Bus Hold Parameters
Series OCT without Calibration Specifications
Series OCT with Calibration at Device Power-Up Specifications
OCT Variation after Calibration at Device Power-Up
Pin Capacitance
Internal Weak Pull-Up Resistor
Hot-Socketing Specifications
Hysteresis Specifications for Schmitt Trigger Input
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Emulated RSDS_E_1R Transmitter Timing Specifications
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications
True LVDS Transmitter Timing
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Visible to Intel only — GUID: mcn1397819620952
Ixiasoft
Differential I/O Standards Specifications
I/O Standard | VCCIO (V) | VID (mV) | VICM (V) 19 | VOD (mV) 20 21 | VOS (V) 20 | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Condition | Max | Min | Typ | Max | Min | Typ | Max | |
LVPECL 22 | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | DMAX ≤ 500 Mbps | 1.8 | — | — | — | — | — | — |
0.55 | 500 Mbps ≤ DMAX ≤ 700 Mbps | 1.8 | ||||||||||||
1.05 | DMAX > 700 Mbps | 1.55 | ||||||||||||
LVDS | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | DMAX ≤ 500 Mbps | 1.8 | 247 | — | 600 | 1.125 | 1.25 | 1.375 |
0.55 | 500 Mbps ≤ DMAX ≤ 700 Mbps | 1.8 | ||||||||||||
1.05 | DMAX > 700 Mbps | 1.55 | ||||||||||||
1.8 V LVDS 23 | 1.71 | 1.8 | 1.89 | 100 | 800 | 0.8 | DMAX ≤ 400 Mbps | 1 | 100 | — | 800 | 0.81 | 0.9 | 0.99 |
BLVDS 24 | 2.375 | 2.5 | 2.625 | 100 | — | — | — | — | — | — | — | — | — | — |
mini-LVDS 25 | 2.375 | 2.5 | 2.625 | — | — | — | — | — | 300 | — | 600 | 1 | 1.2 | 1.4 |
RSDS 25 | 2.375 | 2.5 | 2.625 | — | — | — | — | — | 100 | 200 | 600 | 0.5 | 1.2 | 1.5 |
PPDS (Row I/Os) 25 | 2.375 | 2.5 | 2.625 | — | — | — | — | — | 100 | 200 | 600 | 0.5 | 1.2 | 1.4 |
TMDS26 | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | DMAX ≤ 500 Mbps | 1.8 | — | — | — | — | — | — |
0.55 | 500 Mbps ≤ DMAX ≤ 700 Mbps | 1.8 | ||||||||||||
1.05 | DMAX > 700 Mbps | 1.55 | ||||||||||||
Sub-LVDS 27 | 1.71 | 1.8 | 1.89 | 100 | — | 0.55 | — | 1.25 | 28 | 0.8 | 0.9 | 1 | ||
SLVS | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | — | 1.1 | 28 | 29 | ||||
HiSpi | 2.375 | 2.5 | 2.625 | 100 | — | 0.05 | DMAX ≤ 500 Mbps | 1.8 | — | — | — | — | — | — |
0.55 | 500 Mbps ≤ DMAX ≤ 700 Mbps | 1.8 | ||||||||||||
1.05 | DMAX > 700 Mbps | 1.55 |
19 VIN range: 0 V ≤ VIN ≤ 1.85 V.
20 RL range: 90 ≤ RL ≤ 110 Ω.
21 Low VOD setting is only supported for RSDS standard.
22 LVPECL input standard is only supported at clock input. Output standard is not supported.
23 The 1.8 V LVDS buffers are supported as inputs on all high-speed I/O banks but as outputs only on the bottom banks. The low-speed and high-speed DDR3 I/O banks do not support 1.8 V LVDS. The 1.8 V LVDS I/O standard is supported in industrial- and commercial-grade Intel® MAX® 10 dual supply devices except in packages V36 and V81.
24 No fixed VIN , VOD , and VOS specifications for Bus LVDS (BLVDS). They are dependent on the system topology.
25 Mini-LVDS, RSDS, and Point-to-Point Differential Signaling (PPDS) standards are only supported at the output pins for Intel® MAX® 10 devices.
26 Supported with requirement of an external level shift
27 Sub-LVDS input buffer is using 2.5 V differential buffer.
28 Differential output depends on the values of the external termination resistors.
29 Differential output offset voltage depends on the values of the external termination resistors.
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