Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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JTAG Timing Parameters

Table 49.  JTAG Timing Parameters for Intel® MAX® 10 Devices

The values are based on CL = 10 pF of TDO.

The affected Boundary Scan Test (BST) instructions are SAMPLE/PRELOAD, EXTEST, INTEST, and CHECK_STATUS.

Symbol Parameter Non-BST and non-CONFIG_IO Operation BST and CONFIG_IO Operation Unit
Minimum Maximum Minimum Maximum
tJCP TCK clock period 40 50 ns
tJCH TCK clock high time 20 25 ns
tJCL TCK clock low time 20 25 ns
tJPSU_TDI JTAG port setup time 2 2 ns
tJPSU_TMS JTAG port setup time 3 3 ns
tJPH JTAG port hold time 10 10 ns
tJPCO JTAG port clock to output
  • 15 (for VCCIO = 3.3, 3.0, and 2.5 V)
  • 17 (for VCCIO = 1.8 and 1.5 V)
  • 18 (for VCCIO = 3.3, 3.0, and 2.5 V)
  • 20 (for VCCIO = 1.8 and 1.5 V)
ns
tJPZX JTAG port high impedance to valid output
  • 15 (for VCCIO = 3.3, 3.0, and 2.5 V)
  • 17 (for VCCIO = 1.8 and 1.5 V)
  • 15 (for VCCIO = 3.3, 3.0, and 2.5 V)
  • 17 (for VCCIO = 1.8 and 1.5 V)
ns
tJPXZ JTAG port valid output to high impedance
  • 15 (for VCCIO = 3.3, 3.0, and 2.5 V)
  • 17 (for VCCIO = 1.8 and 1.5 V)
  • 15 (for VCCIO = 3.3, 3.0, and 2.5 V)
  • 17 (for VCCIO = 1.8 and 1.5 V)
ns