Visible to Intel only — GUID: mcn1399899915639
Ixiasoft
Supply Current and Power Consumption
I/O Pin Leakage Current
Bus Hold Parameters
Series OCT without Calibration Specifications
Series OCT with Calibration at Device Power-Up Specifications
OCT Variation after Calibration at Device Power-Up
Pin Capacitance
Internal Weak Pull-Up Resistor
Hot-Socketing Specifications
Hysteresis Specifications for Schmitt Trigger Input
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Emulated RSDS_E_1R Transmitter Timing Specifications
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications
True LVDS Transmitter Timing
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Visible to Intel only — GUID: mcn1399899915639
Ixiasoft
JTAG Timing Parameters
Symbol | Parameter | Non-BST and non-CONFIG_IO Operation | BST and CONFIG_IO Operation | Unit | ||
---|---|---|---|---|---|---|
Minimum | Maximum | Minimum | Maximum | |||
tJCP | TCK clock period | 40 | — | 50 | — | ns |
tJCH | TCK clock high time | 20 | — | 25 | — | ns |
tJCL | TCK clock low time | 20 | — | 25 | — | ns |
tJPSU_TDI | JTAG port setup time | 2 | — | 2 | — | ns |
tJPSU_TMS | JTAG port setup time | 3 | — | 3 | — | ns |
tJPH | JTAG port hold time | 10 | — | 10 | — | ns |
tJPCO | JTAG port clock to output | — |
|
— |
|
ns |
tJPZX | JTAG port high impedance to valid output | — |
|
— |
|
ns |
tJPXZ | JTAG port valid output to high impedance | — |
|
— |
|
ns |