Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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Single Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications

Table 37.  True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Single Supply DevicesTrue RSDS transmitter is only supported at bottom I/O banks. Emulated RSDS transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency (high-speed I/O performance pin) ×10 5 50 5 50 5 50 MHz
×8 5 50 5 50 5 50 MHz
×7 5 50 5 50 5 50 MHz
×4 5 50 5 50 5 50 MHz
×2 5 50 5 50 5 50 MHz
×1 5 100 5 100 5 100 MHz
HSIODR Data rate (high-speed I/O performance pin) ×10 100 100 100 100 100 100 Mbps
×8 80 100 80 100 80 100 Mbps
×7 70 100 70 100 70 100 Mbps
×4 40 100 40 100 40 100 Mbps
×2 20 100 20 100 20 100 Mbps
×1 10 100 10 100 10 100 Mbps
fHSCLK Input clock frequency (low-speed I/O performance pin) ×10 5 50 5 50 5 50 MHz
×8 5 50 5 50 5 50 MHz
×7 5 50 5 50 5 50 MHz
×4 5 50 5 50 5 50 MHz
×2 5 50 5 50 5 50 MHz
×1 5 100 5 100 5 100 MHz
HSIODR Data rate (low-speed I/O performance pin) ×10 100 100 100 100 100 100 Mbps
×8 80 100 80 100 80 100 Mbps
×7 70 100 70 100 70 100 Mbps
×4 40 100 40 100 40 100 Mbps
×2 20 100 20 100 20 100 Mbps
×1 10 100 10 100 10 100 Mbps
tDUTY Duty cycle on transmitter output clock 45 55 45 55 45 55 %
TCCS56 Transmitter channel-to-channel skew 300 300 300 ps
tx Jitter 57 Output jitter (high-speed I/O performance pin) 425 425 425 ps
Output jitter (low-speed I/O performance pin) 470 470 470 ps
tRISE Rise time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tFALL Fall time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration 1 1 1 ms

Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications

Table 38.  True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply DevicesTrue RSDS transmitter is only supported at bottom I/O banks. Emulated RSDS transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency (high-speed I/O performance pin) ×10 5 155 5 155 5 155 MHz
×8 5 155 5 155 5 155 MHz
×7 5 155 5 155 5 155 MHz
×4 5 155 5 155 5 155 MHz
×2 5 155 5 155 5 155 MHz
×1 5 310 5 310 5 310 MHz
HSIODR Data rate (high-speed I/O performance pin) ×10 100 310 100 310 100 310 Mbps
×8 80 310 80 310 80 310 Mbps
×7 70 310 70 310 70 310 Mbps
×4 40 310 40 310 40 310 Mbps
×2 20 310 20 310 20 310 Mbps
×1 10 310 10 310 10 310 Mbps
fHSCLK Input clock frequency (low-speed I/O performance pin) ×10 5 150 5 150 5 150 MHz
×8 5 150 5 150 5 150 MHz
×7 5 150 5 150 5 150 MHz
×4 5 150 5 150 5 150 MHz
×2 5 150 5 150 5 150 MHz
×1 5 300 5 300 5 300 MHz
HSIODR Data rate (low-speed I/O performance pin) ×10 100 300 100 300 100 300 Mbps
×8 80 300 80 300 80 300 Mbps
×7 70 300 70 300 70 300 Mbps
×4 40 300 40 300 40 300 Mbps
×2 20 300 20 300 20 300 Mbps
×1 10 300 10 300 10 300 Mbps
tDUTY Duty cycle on transmitter output clock 45 55 45 55 45 55 %
TCCS58 Transmitter channel-to-channel skew 300 300 300 ps
tx Jitter 59 Output jitter (high-speed I/O performance pin) 425 425 425 ps
Output jitter (low-speed I/O performance pin) 470 470 470 ps
tRISE Rise time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tFALL Fall time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration 1 1 1 ms
56 TCCS specifications apply to I/O banks from the same side only.
57 TX jitter is the jitter induced from core noise and I/O switching noise.
58 TCCS specifications apply to I/O banks from the same side only.
59 TX jitter is the jitter induced from core noise and I/O switching noise.

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