Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 10/31/2022
Public
Document Table of Contents

Programmable IOE Delay for Column Pins

Table 60.  IOE Programmable Delay on Column Pins for Intel® MAX® 10 Devices

The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of the Intel® Quartus® Prime software.

The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Intel® Quartus® Prime software.

Parameter Paths Affected Number of Settings Minimum Offset Maximum Offset Unit
Fast Corner Slow Corner
–I7 –C8, –I8 –A6 –C7 –C8, –I8 –I7 –A7
Input delay from pin to internal cells Pad to I/O dataout to core 7 0 0.81 0.868 1.823 1.802 1.864 1.862 1.912 ns
Input delay from pin to input register Pad to I/O input register 8 0 0.914 0.981 2.06 2.032 2.101 2.102 2.161 ns
Delay from output register to output pin I/O output register to pad 2 0 0.435 0.466 0.971 0.97 1.013 1.001 1.028 ns

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