Intel® MAX® 10 FPGA Device Datasheet

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ID 683794
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents
Intel® MAX® 10 FPGA Device Datasheet
Intel® MAX® 10 FPGA Device Datasheet
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® MAX® 10 FPGA Device Datasheet
Electrical Characteristics
Operating Conditions
Operating Conditions
Absolute Maximum Ratings Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame Recommended Operating Conditions Programming/Erasure Specifications DC Characteristics I/O Standards Specifications
Absolute Maximum Ratings
Single Supply Devices Absolute Maximum Ratings Dual Supply Devices Absolute Maximum Ratings Absolute Maximum Ratings
Recommended Operating Conditions
Single Supply Devices Power Supplies Recommended Operating Conditions Dual Supply Devices Power Supplies Recommended Operating Conditions Recommended Operating Conditions
DC Characteristics
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Parameters Series OCT without Calibration Specifications Series OCT with Calibration at Device Power-Up Specifications OCT Variation after Calibration at Device Power-Up Pin Capacitance Internal Weak Pull-Up Resistor Hot-Socketing Specifications Hysteresis Specifications for Schmitt Trigger Input
I/O Standards Specifications
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics
Core Performance Specifications Periphery Performance Specifications
Core Performance Specifications
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Performance Specifications Internal Oscillator Specifications UFM Performance Specifications ADC Performance Specifications
ADC Performance Specifications
Single Supply Devices ADC Performance Specifications Dual Supply Devices ADC Performance Specifications
Periphery Performance Specifications
High-Speed I/O Specifications Memory Standards Supported by the Soft Memory Controller Memory Output Clock Jitter Specifications
High-Speed I/O Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications True LVDS Transmitter Timing Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Configuration Specifications
JTAG Timing Parameters Remote System Upgrade Circuitry Timing Specifications User Watchdog Internal Circuitry Timing Specifications Uncompressed Raw Binary File (.rbf) Sizes Internal Configuration Time Internal Configuration Timing Parameter
Programmable IOE Delay
Programmable IOE Delay On Row Pins Programmable IOE Delay for Column Pins
Intel® MAX® 10 FPGA Device Datasheet

Programmable IOE Delay for Column Pins

Table 60.  IOE Programmable Delay on Column Pins for Intel® MAX® 10 Devices

The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of the Intel® Quartus® Prime software.

The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Intel® Quartus® Prime software.

Parameter Paths Affected Number of Settings Minimum Offset Maximum Offset Unit
Fast Corner Slow Corner
–I7 –C8, –I8 –A6 –C7 –C8, –I8 –I7 –A7
Input delay from pin to internal cells Pad to I/O dataout to core 7 0 0.81 0.868 1.823 1.802 1.864 1.862 1.912 ns
Input delay from pin to input register Pad to I/O input register 8 0 0.914 0.981 2.06 2.032 2.101 2.102 2.161 ns
Delay from output register to output pin I/O output register to pad 2 0 0.435 0.466 0.971 0.97 1.013 1.001 1.028 ns
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