Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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Single Supply Devices LVDS Receiver Timing Specifications

Table 45.  LVDS Receiver Timing Specifications for Intel® MAX® 10 Single Supply Devices LVDS receivers are supported at all banks.
Symbol Parameter Mode –C7, –I7 –A7 –C8 Unit
Min Max Min Max Min Max
fHSCLK Input clock frequency (high-speed I/O performance pin) ×10 5 145 5 100 5 100 MHz
×8 5 145 5 100 5 100 MHz
×7 5 145 5 100 5 100 MHz
×4 5 145 5 100 5 100 MHz
×2 5 145 5 100 5 100 MHz
×1 5 290 5 200 5 200 MHz
HSIODR Data rate (high-speed I/O performance pin) ×10 100 290 100 200 100 200 Mbps
×8 80 290 80 200 80 200 Mbps
×7 70 290 70 200 70 200 Mbps
×4 40 290 40 200 40 200 Mbps
×2 20 290 20 200 20 200 Mbps
×1 10 290 10 200 10 200 Mbps
fHSCLK Input clock frequency (low-speed I/O performance pin) ×10 5 100 5 100 5 100 MHz
×8 5 100 5 100 5 100 MHz
×7 5 100 5 100 5 100 MHz
×4 5 100 5 100 5 100 MHz
×2 5 100 5 100 5 100 MHz
×1 5 200 5 200 5 200 MHz
HSIODR Data rate (low-speed I/O performance pin) ×10 100 200 100 200 100 200 Mbps
×8 80 200 80 200 80 200 Mbps
×7 70 200 70 200 70 200 Mbps
×4 40 200 40 200 40 200 Mbps
×2 20 200 20 200 20 200 Mbps
×1 10 200 10 200 10 200 Mbps
SW Sampling window (high-speed I/O performance pin) 910 910 910 ps
Sampling window (low-speed I/O performance pin) 1,110 1,110 1,110 ps
tx Jitter 72 Input jitter 1,000 1,000 1,000 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration 1 1 1 ms

Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

Table 46.  LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel® MAX® 10 Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS receivers are supported at all banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Max Min Max Min Max
fHSCLK Input clock frequency (high-speed I/O performance pin) ×10 5 350 5 320 5 320 MHz
×8 5 360 5 320 5 320 MHz
×7 5 350 5 320 5 320 MHz
×4 5 360 5 320 5 320 MHz
×2 5 360 5 320 5 320 MHz
×1 5 360 5 320 5 320 MHz
HSIODR Data rate (high-speed I/O performance pin) ×10 100 700 100 640 100 640 Mbps
×8 80 720 80 640 80 640 Mbps
×7 70 700 70 640 70 640 Mbps
×4 40 720 40 640 40 640 Mbps
×2 20 720 20 640 20 640 Mbps
×1 10 360 10 320 10 320 Mbps
fHSCLK Input clock frequency (low-speed I/O performance pin) ×10 5 150 5 150 5 150 MHz
×8 5 150 5 150 5 150 MHz
×7 5 150 5 150 5 150 MHz
×4 5 150 5 150 5 150 MHz
×2 5 150 5 150 5 150 MHz
×1 5 300 5 300 5 300 MHz
HSIODR Data rate (low-speed I/O performance pin) ×10 100 300 100 300 100 300 Mbps
×8 80 300 80 300 80 300 Mbps
×7 70 300 70 300 70 300 Mbps
×4 40 300 40 300 40 300 Mbps
×2 20 300 20 300 20 300 Mbps
×1 10 300 10 300 10 300 Mbps
SW Sampling window (high-speed I/O performance pin) 510 510 510 ps
Sampling window (low-speed I/O performance pin) 910 910 910 ps
tx Jitter 73 Input jitter 500 500 500 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration 1 1 1 ms
72 TX jitter is the jitter induced from core noise and I/O switching noise.
73 TX jitter is the jitter induced from core noise and I/O switching noise.