Intel® MAX® 10 FPGA Device Datasheet

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ID 683794
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents
Intel® MAX® 10 FPGA Device Datasheet
Intel® MAX® 10 FPGA Device Datasheet
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® MAX® 10 FPGA Device Datasheet
Electrical Characteristics
Operating Conditions
Operating Conditions
Absolute Maximum Ratings Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame Recommended Operating Conditions Programming/Erasure Specifications DC Characteristics I/O Standards Specifications
Absolute Maximum Ratings
Single Supply Devices Absolute Maximum Ratings Dual Supply Devices Absolute Maximum Ratings Absolute Maximum Ratings
Recommended Operating Conditions
Single Supply Devices Power Supplies Recommended Operating Conditions Dual Supply Devices Power Supplies Recommended Operating Conditions Recommended Operating Conditions
DC Characteristics
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Parameters Series OCT without Calibration Specifications Series OCT with Calibration at Device Power-Up Specifications OCT Variation after Calibration at Device Power-Up Pin Capacitance Internal Weak Pull-Up Resistor Hot-Socketing Specifications Hysteresis Specifications for Schmitt Trigger Input
I/O Standards Specifications
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics
Core Performance Specifications Periphery Performance Specifications
Core Performance Specifications
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Performance Specifications Internal Oscillator Specifications UFM Performance Specifications ADC Performance Specifications
ADC Performance Specifications
Single Supply Devices ADC Performance Specifications Dual Supply Devices ADC Performance Specifications
Periphery Performance Specifications
High-Speed I/O Specifications Memory Standards Supported by the Soft Memory Controller Memory Output Clock Jitter Specifications
High-Speed I/O Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications True LVDS Transmitter Timing Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Configuration Specifications
JTAG Timing Parameters Remote System Upgrade Circuitry Timing Specifications User Watchdog Internal Circuitry Timing Specifications Uncompressed Raw Binary File (.rbf) Sizes Internal Configuration Time Internal Configuration Timing Parameter
Programmable IOE Delay
Programmable IOE Delay On Row Pins Programmable IOE Delay for Column Pins
Intel® MAX® 10 FPGA Device Datasheet

LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

Single Supply Devices LVDS Receiver Timing Specifications

Table 46.  LVDS Receiver Timing Specifications for Intel® MAX® 10 Single Supply Devices LVDS receivers are supported at all banks.
Symbol Parameter Mode –C7, –I7 –A7 –C8, –I8 Unit
Min Max Min Max Min Max
fHSCLK Input clock frequency (high-speed I/O performance pin) ×10 5 145 5 100 5 100 MHz
×8 5 145 5 100 5 100 MHz
×7 5 145 5 100 5 100 MHz
×4 5 145 5 100 5 100 MHz
×2 5 145 5 100 5 100 MHz
×1 5 290 5 200 5 200 MHz
HSIODR Data rate (high-speed I/O performance pin) ×10 100 290 100 200 100 200 Mbps
×8 80 290 80 200 80 200 Mbps
×7 70 290 70 200 70 200 Mbps
×4 40 290 40 200 40 200 Mbps
×2 20 290 20 200 20 200 Mbps
×1 10 290 10 200 10 200 Mbps
fHSCLK Input clock frequency (low-speed I/O performance pin) ×10 5 100 5 100 5 100 MHz
×8 5 100 5 100 5 100 MHz
×7 5 100 5 100 5 100 MHz
×4 5 100 5 100 5 100 MHz
×2 5 100 5 100 5 100 MHz
×1 5 200 5 200 5 200 MHz
HSIODR Data rate (low-speed I/O performance pin) ×10 100 200 100 200 100 200 Mbps
×8 80 200 80 200 80 200 Mbps
×7 70 200 70 200 70 200 Mbps
×4 40 200 40 200 40 200 Mbps
×2 20 200 20 200 20 200 Mbps
×1 10 200 10 200 10 200 Mbps
SW Sampling window (high-speed I/O performance pin) — — 910 — 910 — 910 ps
Sampling window (low-speed I/O performance pin) — — 1,110 — 1,110 — 1,110 ps
tx Jitter 75 Input jitter — — 1,000 — 1,000 — 1,000 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration — — 1 — 1 — 1 ms

Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications

Table 47.  LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel® MAX® 10 Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS receivers are supported at all banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8, –I8 Unit
Min Max Min Max Min Max
fHSCLK Input clock frequency (high-speed I/O performance pin) ×10 5 350 5 320 5 320 MHz
×8 5 360 5 320 5 320 MHz
×7 5 350 5 320 5 320 MHz
×4 5 360 5 320 5 320 MHz
×2 5 360 5 320 5 320 MHz
×1 5 360 5 320 5 320 MHz
HSIODR Data rate (high-speed I/O performance pin) ×10 100 700 100 640 100 640 Mbps
×8 80 720 80 640 80 640 Mbps
×7 70 700 70 640 70 640 Mbps
×4 40 720 40 640 40 640 Mbps
×2 20 720 20 640 20 640 Mbps
×1 10 360 10 320 10 320 Mbps
fHSCLK Input clock frequency (low-speed I/O performance pin) ×10 5 150 5 150 5 150 MHz
×8 5 150 5 150 5 150 MHz
×7 5 150 5 150 5 150 MHz
×4 5 150 5 150 5 150 MHz
×2 5 150 5 150 5 150 MHz
×1 5 300 5 300 5 300 MHz
HSIODR Data rate (low-speed I/O performance pin) ×10 100 300 100 300 100 300 Mbps
×8 80 300 80 300 80 300 Mbps
×7 70 300 70 300 70 300 Mbps
×4 40 300 40 300 40 300 Mbps
×2 20 300 20 300 20 300 Mbps
×1 10 300 10 300 10 300 Mbps
SW Sampling window (high-speed I/O performance pin) — — 510 — 510 — 510 ps
Sampling window (low-speed I/O performance pin) — — 910 — 910 — 910 ps
tx Jitter 76 Input jitter — — 500 — 500 — 500 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration — — 1 — 1 — 1 ms
Table 48.  True 1.8 V LVDS Receiver Timing Specifications for Intel® MAX® 10 Dual Supply Devices True 1.8 V LVDS receiver is only supported at the high-speed I/O banks, except high-speed DDR3 I/O banks.
Symbol Parameter Mode –I6, –C7, –I7 –C8, –I8 Unit
Min Max Min Max
fHSCLK Input clock frequency (bottom-bank I/O performance pin) ×10 5 200 5 200 MHz
×8 5 200 5 200 MHz
×7 5 200 5 200 MHz
×4 5 200 5 200 MHz
×2 5 200 5 200 MHz
×1 5 100 5 100 MHz
HSIODR Data rate (bottom-bank I/O performance pin) ×10 100 400 100 400 Mbps
×8 80 400 80 400 Mbps
×7 70 400 70 400 Mbps
×4 40 400 40 400 Mbps
×2 20 400 20 400 Mbps
×1 10 200 10 200 Mbps
SW Sampling window (high-speed I/O performance pin) — — 510 — 510 ps
tx Jitter 77 Input jitter — — 500 — 500 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration — — 1 — 1 ms
75 TX jitter is the jitter induced from core noise and I/O switching noise.
76 TX jitter is the jitter induced from core noise and I/O switching noise.
77 TX jitter is the jitter induced from core noise and I/O switching noise.
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