Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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Emulated RSDS_E_1R Transmitter Timing Specifications

Table 39.  Emulated RSDS_E_1R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply DevicesEmulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency (high-speed I/O performance pin) ×10 5 85 5 85 5 85 MHz
×8 5 85 5 85 5 85 MHz
×7 5 85 5 85 5 85 MHz
×4 5 85 5 85 5 85 MHz
×2 5 85 5 85 5 85 MHz
×1 5 170 5 170 5 170 MHz
HSIODR Data rate (high-speed I/O performance pin) ×10 100 170 100 170 100 170 Mbps
×8 80 170 80 170 80 170 Mbps
×7 70 170 70 170 70 170 Mbps
×4 40 170 40 170 40 170 Mbps
×2 20 170 20 170 20 170 Mbps
×1 10 170 10 170 10 170 Mbps
fHSCLK Input clock frequency (low-speed I/O performance pin) ×10 5 85 5 85 5 85 MHz
×8 5 85 5 85 5 85 MHz
×7 5 85 5 85 5 85 MHz
×4 5 85 5 85 5 85 MHz
×2 5 85 5 85 5 85 MHz
×1 5 170 5 170 5 170 MHz
HSIODR Data rate (low-speed I/O performance pin) ×10 100 170 100 170 100 170 Mbps
×8 80 170 80 170 80 170 Mbps
×7 70 170 70 170 70 170 Mbps
×4 40 170 40 170 40 170 Mbps
×2 20 170 20 170 20 170 Mbps
×1 10 170 10 170 10 170 Mbps
tDUTY Duty cycle on transmitter output clock 45 55 45 55 45 55 %
TCCS60 Transmitter channel-to-channel skew 300 300 300 ps
tx Jitter 61 Output jitter (high-speed I/O performance pin) 425 425 425 ps
Output jitter (low-speed I/O performance pin) 470 470 470 ps
tRISE Rise time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tFALL Fall time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration 1 1 1 ms
60 TCCS specifications apply to I/O banks from the same side only.
61 TX jitter is the jitter induced from core noise and I/O switching noise.

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