Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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Single Supply Devices True LVDS Transmitter Timing Specifications

Table 41.  True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Single Supply DevicesTrue LVDS transmitter is only supported at the bottom I/O banks.
Symbol Parameter Mode –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency ×10 5 145 5 100 5 100 MHz
×8 5 145 5 100 5 100 MHz
×7 5 145 5 100 5 100 MHz
×4 5 145 5 100 5 100 MHz
×2 5 145 5 100 5 100 MHz
×1 5 290 5 200 5 200 MHz
HSIODR Data rate ×10 100 290 100 200 100 200 Mbps
×8 80 290 80 200 80 200 Mbps
×7 70 290 70 200 70 200 Mbps
×4 40 290 40 200 40 200 Mbps
×2 20 290 20 200 20 200 Mbps
×1 10 290 10 200 10 200 Mbps
tDUTY Duty cycle on transmitter output clock 45 55 45 55 45 55 %
TCCS64 Transmitter channel-to-channel skew 300 300 300 ps
tx Jitter 65 Output jitter 1,000 1,000 1,000 ps
tRISE Rise time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tFALL Fall time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration 1 1 1 ms

Dual Supply Devices True LVDS Transmitter Timing Specifications

Table 42.  True LVDS Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply DevicesTrue LVDS transmitter is only supported at the bottom I/O banks.
Symbol Parameter Mode –I6 –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency ×10 5 360 5 340 5 310 5 300 MHz
×8 5 360 5 360 5 320 5 320 MHz
×7 5 360 5 340 5 310 5 300 MHz
×4 5 360 5 350 5 320 5 320 MHz
×2 5 360 5 350 5 320 5 320 MHz
×1 5 360 5 350 5 320 5 320 MHz
HSIODR Data rate ×10 100 720 100 680 100 620 100 600 Mbps
×8 80 720 80 720 80 640 80 640 Mbps
×7 70 720 70 680 70 620 70 600 Mbps
×4 40 720 40 700 40 640 40 640 Mbps
×2 20 720 20 700 20 640 20 640 Mbps
×1 10 360 10 350 10 320 10 320 Mbps
tDUTY Duty cycle on transmitter output clock 45 55 45 55 45 55 45 55 %
TCCS66 Transmitter channel-to-channel skew 300 300 300 300 ps
tx Jitter 67 Output jitter 380 380 380 380 ps
tRISE Rise time 20 – 80%, CLOAD = 5 pF 500 500 500 500 ps
tFALL Fall time 20 – 80%, CLOAD = 5 pF 500 500 500 500 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration 1 1 1 1 ms
64 TCCS specifications apply to I/O banks from the same side only.
65 TX jitter is the jitter induced from core noise and I/O switching noise.
66 TCCS specifications apply to I/O banks from the same side only.
67 TX jitter is the jitter induced from core noise and I/O switching noise.

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