Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
Public
Download
Document Table of Contents

Pin Capacitance

Table 16.  Pin Capacitance for Intel® MAX® 10 Devices
Symbol Parameter Maximum Unit
CIOB Input capacitance on bottom I/O pins 8 pF
CIOLRT Input capacitance on left/right/top I/O pins 7 pF
CLVDSB Input capacitance on bottom I/O pins with dedicated LVDS output 9 8 pF
CADCL Input capacitance on left I/O pins with ADC input 10 9 pF
CVREFLRT Input capacitance on left/right/top dual purpose VREF pin when used as VREF or user I/O pin 11 48 pF
CVREFB Input capacitance on bottom dual purpose VREF pin when used as VREF or user I/O pin 50 pF
CCLKB Input capacitance on bottom dual purpose clock input pins 12 7 pF
CCLKLRT Input capacitance on left/right/top dual purpose clock input pins 12 6 pF
9 Dedicated LVDS output buffer is only available at bottom I/O banks.
10 ADC pins are only available at left I/O banks.
11 When VREF pin is used as regular input or output, Fmax performance is reduced due to higher pin capacitance. Using the VREF pin capacitance specification from device datasheet, perform SI analysis on your board setup to determine the Fmax of your system.
12 10M40 and 10M50 devices have dual purpose clock input pins at top/bottom I/O banks.