Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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OCT Variation after Calibration at Device Power-Up

The OCT resistance may vary with the variation of temperature and voltage after calibration at device power-up.

Use the following table and equation to determine the final OCT resistance considering the variations after calibration at device power-up.

Table 15.  OCT Variation after Calibration at Device Power-Up for Intel® MAX® 10 DevicesThis table lists the change percentage of the OCT resistance with voltage and temperature.
Description Nominal Voltage dR/dT (%/°C) dR/dV (%/mV)
OCT variation after calibration at device power-up 3.00 0.25 –0.027
2.50 0.245 –0.04
1.80 0.242 –0.079
1.50 0.235 –0.125
1.35 0.229 –0.16
1.20 0.197 –0.208
Figure 1. Equation for OCT Resistance after Calibration at Device Power-Up

The definitions for equation are as follows:

  • T1 is the initial temperature.
  • T2 is the final temperature.
  • MF is multiplication factor.
  • Rinitial is initial resistance.
  • Rfinal is final resistance.
  • Subscript x refers to both V and T.
  • ∆RV is variation of resistance with voltage.
  • ∆RT is variation of resistance with temperature.
  • dR/dT is the change percentage of resistance with temperature after calibration at device power-up.
  • dR/dV is the change percentage of resistance with voltage after calibration at device power-up.
  • V1 is the initial voltage.
  • V2 is final voltage.

The following figure shows the example to calculate the change of 50 Ω I/O impedance from 25°C at 3.0 V to 85°C at 3.15 V.

Figure 2. Example for OCT Resistance Calculation after Calibration at Device Power-Up

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