Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications

Table 21.  Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel® MAX® 10 Devices
I/O Standard VCCIO (V) VREF (V) VTT (V)  15
Min Typ Max Min Typ Max Min Typ Max
SSTL-2 Class I, II 2.375 2.5 2.625 1.19 1.25 1.31 VREF – 0.04 VREF VREF + 0.04
SSTL-18 Class I, II 1.7 1.8 1.9 0.833 0.9 0.969 VREF – 0.04 VREF VREF + 0.04
SSTL-15 Class I, II 1.425 1.5 1.575 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
SSTL-135 Class I, II 1.283 1.35 1.45 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 0.85 0.9 0.95
HSTL-15 Class I, II 1.425 1.5 1.575 0.71 0.75 0.79 0.71 0.75 0.79
HSTL-12 Class I, II 1.14 1.2 1.26 0.48 × VCCIO 16 0.5 × VCCIO 16 0.52 × VCCIO 16 0.5 × VCCIO
0.47 × VCCIO   17 0.5 × VCCIO  17 0.53 × VCCIO  17
HSUL-12 1.14 1.2 1.3 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
15 VTT of transmitting device must track VREF of the receiving device.
16 Value shown refers to DC input reference voltage, VREF(DC).
17 Value shown refers to AC input reference voltage, VREF(AC).