Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
Public
Download
Document Table of Contents

True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications

Table 36.  True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel® MAX® 10 Dual Supply DevicesTrue PPDS transmitter is only supported at bottom I/O banks. Emulated PPDS transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency (high-speed I/O performance pin) ×10 5 155 5 155 5 155 MHz
×8 5 155 5 155 5 155 MHz
×7 5 155 5 155 5 155 MHz
×4 5 155 5 155 5 155 MHz
×2 5 155 5 155 5 155 MHz
×1 5 310 5 310 5 310 MHz
HSIODR Data rate (high-speed I/O performance pin) ×10 100 310 100 310 100 310 Mbps
×8 80 310 80 310 80 310 Mbps
×7 70 310 70 310 70 310 Mbps
×4 40 310 40 310 40 310 Mbps
×2 20 310 20 310 20 310 Mbps
×1 10 310 10 310 10 310 Mbps
fHSCLK Input clock frequency (low-speed I/O performance pin) ×10 5 150 5 150 5 150 MHz
×8 5 150 5 150 5 150 MHz
×7 5 150 5 150 5 150 MHz
×4 5 150 5 150 5 150 MHz
×2 5 150 5 150 5 150 MHz
×1 5 300 5 300 5 300 MHz
HSIODR Data rate (low-speed I/O performance pin) ×10 100 300 100 300 100 300 Mbps
×8 80 300 80 300 80 300 Mbps
×7 70 300 70 300 70 300 Mbps
×4 40 300 40 300 40 300 Mbps
×2 20 300 20 300 20 300 Mbps
×1 10 300 10 300 10 300 Mbps
tDUTY Duty cycle on transmitter output clock 45 55 45 55 45 55 %
TCCS54 Transmitter channel-to-channel skew 300 300 300 ps
tx Jitter 55 Output jitter (high-speed I/O performance pin) 425 425 425 ps
Output jitter (low-speed I/O performance pin) 470 470 470 ps
tRISE Rise time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tFALL Fall time 20 – 80%, CLOAD = 5 pF 500 500 500 ps
tLOCK Time required for the PLL to lock, after CONF_DONE signal goes high, indicating the completion of device configuration 1 1 1 ms
54 TCCS specifications apply to I/O banks from the same side only.
55 TX jitter is the jitter induced from core noise and I/O switching noise.