Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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Differential HSTL and HSUL I/O Standards Specifications

Differential HSTL requires a VREF input.

Table 24.  Differential HSTL and HSUL I/O Standards Specifications for Intel® MAX® 10 Devices
I/O Standard VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V)
Min Typ Max Min Max Min Typ Max Min Typ Max Min
HSTL-18 Class I, II 1.71 1.8 1.89 0.2 0.85 0.95 0.85 0.95 0.4
HSTL-15 Class I, II 1.425 1.5 1.575 0.2 0.71 0.79 0.71 0.79 0.4
HSTL-12 Class I, II 1.14 1.2 1.26 0.16 VCCIO 0.48 × VCCIO 0.5 × VCCIO 0.52 × VCCIO 0.48 × VCCIO 0.5 × VCCIO 0.52 × VCCIO 0.3
HSUL-12 1.14 1.2 1.3 0.26 0.5 × VCCIO – 0.12 0.5 × VCCIO 0.5 × VCCIO + 0.12 0.4 × VCCIO 0.5 × VCCIO 0.6 × VCCIO 0.44