Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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Bus Hold Parameters

Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode.

Table 12.  Bus Hold Parameters for Intel® MAX® 10 Devices
Parameter Condition VCCIO (V) Unit
1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold low, sustaining current VIN > VIL (maximum) 8 12 30 50 70 70 µA
Bus-hold high, sustaining current VIN < VIH (minimum) –8 –12 –30 –50 –70 –70 µA
Bus-hold low, overdrive current 0 V < VIN < VCCIO 125 175 200 300 500 500 µA
Bus-hold high, overdrive current 0 V < VIN < VCCIO –125 –175 –200 –300 –500 –500 µA
Bus-hold trip point 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V