Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 10/31/2022
Document Table of Contents

I/O Timing

The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis.

The Intel® Quartus® Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specific device and design after you complete place-and-route.

Table 58.  I/O Timing for Intel® MAX® 10 DevicesThese I/O timing parameters are for the 3.3-V LVTTL I/O standard with the maximum drive strength and fast slew rate for 10M08DAF484 device.
Symbol Parameter –C7, –I7 –C8, –I8 Unit
Tsu Global clock setup time –0.750 –0.808 ns
Th Global clock hold time 1.180 1.215 ns
Tco Global clock to output delay 5.131 5.575 ns
Tpd Best case pin-to-pin propagation delay through one LUT 4.907 5.467 ns

Did you find the information on this page useful?

Characters remaining:

Feedback Message