Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Parameters Series OCT without Calibration Specifications Series OCT with Calibration at Device Power-Up Specifications OCT Variation after Calibration at Device Power-Up Pin Capacitance Internal Weak Pull-Up Resistor Hot-Socketing Specifications Hysteresis Specifications for Schmitt Trigger Input
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications True LVDS Transmitter Timing Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
|R_PU||Value of I/O pin (dedicated and dual-purpose) pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled||VCCIO = 3.3 V ± 5%||7||12||34||kΩ|
|VCCIO = 3.0 V ± 5%||8||13||37||kΩ|
|VCCIO = 2.5 V ± 5%||10||15||46||kΩ|
|VCCIO = 1.8 V ± 5%||16||25||75||kΩ|
|VCCIO = 1.5 V ± 5%||20||36||106||kΩ|
|VCCIO = 1.2 V ± 5%||33||82||179||kΩ|
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