Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Parameters Series OCT without Calibration Specifications Series OCT with Calibration at Device Power-Up Specifications OCT Variation after Calibration at Device Power-Up Pin Capacitance Internal Weak Pull-Up Resistor Hot-Socketing Specifications Hysteresis Specifications for Schmitt Trigger Input
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications True LVDS Transmitter Timing Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Dual Supply Devices Power Supplies Recommended Operating Conditions
|VCC||Supply voltage for core and periphery||—||1.15||1.2||1.25||V|
|VCCIO 3||Supply voltage for input and output buffers||3.3 V||3.135||3.3||3.465||V|
|VCCA 4||Supply voltage for PLL regulator (analog)||—||2.375||2.5||2.625||V|
|VCCD_PLL 5||Supply voltage for PLL regulator (digital)||—||1.15||1.2||1.25||V|
|VCCA_ADC||Supply voltage for ADC analog block||—||2.375||2.5||2.625||V|
|VCCINT||Supply voltage for ADC digital block||—||1.15||1.2||1.25||V|
3 VCCIO for all I/O banks must be powered up during user mode because VCCIO I/O banks are used for the ADC and I/O functionalities.
4 All VCCA pins must be powered to 2.5 V (even when PLLs are not used), and must be powered up and powered down at the same time.
5 VCCD_PLL must always be connected to VCC through a decoupling capacitor and ferrite bead.
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