Intel® MAX® 10 FPGA Device Datasheet

ID 683794
Date 11/01/2021
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PLL Specifications

Table 27.  PLL Specifications for Intel® MAX® 10 Devices VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
Symbol Parameter Condition Min Typ Max Unit
fIN   29 Input clock frequency 5 472.5 MHz
fINPFD Phase frequency detector (PFD) input frequency 5 325 MHz
fVCO  30 PLL internal voltage-controlled oscillator (VCO) operating range 600 1300 MHz
fINDUTY Input clock duty cycle 40 60 %
tINJITTER_CCJ  31 Input clock cycle-to-cycle jitter FINPFD ≥ 100 MHz 0.15 UI
FINPFD < 100 MHz ±750 ps
fOUT_EXT  29 PLL output frequency for external clock output 472.5 MHz
fOUT PLL output frequency to global clock –6 speed grade 472.5 MHz
–7 speed grade 450 MHz
–8 speed grade 402.5 MHz
tOUTDUTY Duty cycle for external clock output Duty cycle set to 50% 45 50 55 %
tLOCK Time required to lock from end of device configuration 1 ms
tDLOCK Time required to lock dynamically After switchover, reconfiguring any non-post-scale counters or delays, or when areset is deasserted 1 ms
tOUTJITTER_PERIOD_IO   32 Regular I/O period jitter FOUT ≥ 100 MHz 650 ps
FOUT < 100 MHz 75 mUI
tOUTJITTER_CCJ_IO  32 Regular I/O cycle-to-cycle jitter FOUT ≥ 100 MHz 650 ps
FOUT < 100 MHz 75 mUI
tPLL_PSERR Accuracy of PLL phase shift ±50 ps
tARESET Minimum pulse width on areset signal. 10 ns
tCONFIGPLL Time required to reconfigure scan chains for PLLs 3.5  33 SCANCLK cycles
fSCANCLK scanclk frequency 100 MHz
Table 28.  PLL Specifications for Intel® MAX® 10 Single Supply DevicesFor V36 package, the PLL specification is based on single supply devices.
Symbol Parameter Condition Max Unit
tOUTJITTER_PERIOD_DEDCLK  32   Dedicated clock output period jitter FOUT ≥ 100 MHz 660 ps
FOUT < 100 MHz 66 mUI
tOUTJITTER_CCJ_DEDCLK  32   Dedicated clock output cycle-to-cycle jitter FOUT ≥ 100 MHz 660 ps
FOUT < 100 MHz 66 mUI
Table 29.  PLL Specifications for Intel® MAX® 10 Dual Supply Devices
Symbol Parameter Condition Max Unit
tOUTJITTER_PERIOD_DEDCLK  32 Dedicated clock output period jitter FOUT ≥ 100 MHz 300 ps
FOUT < 100 MHz 30 mUI
tOUTJITTER_CCJ_DEDCLK  32 Dedicated clock output cycle-to-cycle jitter FOUT ≥ 100 MHz 300 ps
FOUT < 100 MHz 30 mUI
29 This parameter is limited in the Intel® Quartus® Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
30 The VCO frequency reported by the Intel® Quartus® Prime software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
31 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
32 Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
33 With 100 MHz scanclk frequency.