Visible to Intel only — GUID: mcn1397897761093
Ixiasoft
Supply Current and Power Consumption
I/O Pin Leakage Current
Bus Hold Parameters
Series OCT without Calibration Specifications
Series OCT with Calibration at Device Power-Up Specifications
OCT Variation after Calibration at Device Power-Up
Pin Capacitance
Internal Weak Pull-Up Resistor
Hot-Socketing Specifications
Hysteresis Specifications for Schmitt Trigger Input
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Emulated RSDS_E_1R Transmitter Timing Specifications
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications
True LVDS Transmitter Timing
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Visible to Intel only — GUID: mcn1397897761093
Ixiasoft
PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN 30 | Input clock frequency | — | 5 | — | 472.5 | MHz |
fINPFD | Phase frequency detector (PFD) input frequency | — | 5 | — | 325 | MHz |
fVCO 31 | PLL internal voltage-controlled oscillator (VCO) operating range | — | 600 | — | 1300 | MHz |
fINDUTY | Input clock duty cycle | — | 40 | — | 60 | % |
tINJITTER_CCJ 32 | Input clock cycle-to-cycle jitter | FINPFD ≥ 100 MHz | — | — | 0.15 | UI |
FINPFD < 100 MHz | — | — | ±750 | ps | ||
fOUT_EXT 30 | PLL output frequency for external clock output | — | — | — | 472.5 | MHz |
fOUT | PLL output frequency to global clock | –6 speed grade | — | — | 472.5 | MHz |
–7 speed grade | — | — | 450 | MHz | ||
–8 speed grade | — | — | 402.5 | MHz | ||
tOUTDUTY | Duty cycle for external clock output | Duty cycle set to 50% | 45 | 50 | 55 | % |
tLOCK | Time required to lock from end of device configuration | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically | After switchover, reconfiguring any non-post-scale counters or delays, or when areset is deasserted | — | — | 1 | ms |
tOUTJITTER_PERIOD_IO 33 | Regular I/O period jitter | FOUT ≥ 100 MHz | — | — | 650 | ps |
FOUT < 100 MHz | — | — | 75 | mUI | ||
tOUTJITTER_CCJ_IO 33 | Regular I/O cycle-to-cycle jitter | FOUT ≥ 100 MHz | — | — | 650 | ps |
FOUT < 100 MHz | — | — | 75 | mUI | ||
tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on areset signal. | — | 10 | — | — | ns |
tCONFIGPLL | Time required to reconfigure scan chains for PLLs | — | — | 3.5 34 | — | SCANCLK cycles |
fSCANCLK | scanclk frequency | — | — | — | 100 | MHz |
Symbol | Parameter | Condition | Max | Unit |
---|---|---|---|---|
tOUTJITTER_PERIOD_DEDCLK 33 | Dedicated clock output period jitter | FOUT ≥ 100 MHz | 660 | ps |
FOUT < 100 MHz | 66 | mUI | ||
tOUTJITTER_CCJ_DEDCLK 33 | Dedicated clock output cycle-to-cycle jitter | FOUT ≥ 100 MHz | 660 | ps |
FOUT < 100 MHz | 66 | mUI |
Symbol | Parameter | Condition | Max | Unit |
---|---|---|---|---|
tOUTJITTER_PERIOD_DEDCLK 33 | Dedicated clock output period jitter | FOUT ≥ 100 MHz | 300 | ps |
FOUT < 100 MHz | 30 | mUI | ||
tOUTJITTER_CCJ_DEDCLK 33 | Dedicated clock output cycle-to-cycle jitter | FOUT ≥ 100 MHz | 300 | ps |
FOUT < 100 MHz | 30 | mUI |
30 This parameter is limited in the Intel® Quartus® Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
31 The VCO frequency reported by the Intel® Quartus® Prime software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
32 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
33 Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
34 With 100 MHz scanclk frequency.
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