Intel® MAX® 10 FPGA Device Datasheet

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ID 683794
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents
Intel® MAX® 10 FPGA Device Datasheet
Intel® MAX® 10 FPGA Device Datasheet
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® MAX® 10 FPGA Device Datasheet
Electrical Characteristics
Operating Conditions
Operating Conditions
Absolute Maximum Ratings Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame Recommended Operating Conditions Programming/Erasure Specifications DC Characteristics I/O Standards Specifications
Absolute Maximum Ratings
Single Supply Devices Absolute Maximum Ratings Dual Supply Devices Absolute Maximum Ratings Absolute Maximum Ratings
Recommended Operating Conditions
Single Supply Devices Power Supplies Recommended Operating Conditions Dual Supply Devices Power Supplies Recommended Operating Conditions Recommended Operating Conditions
DC Characteristics
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Parameters Series OCT without Calibration Specifications Series OCT with Calibration at Device Power-Up Specifications OCT Variation after Calibration at Device Power-Up Pin Capacitance Internal Weak Pull-Up Resistor Hot-Socketing Specifications Hysteresis Specifications for Schmitt Trigger Input
I/O Standards Specifications
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics
Core Performance Specifications Periphery Performance Specifications
Core Performance Specifications
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Performance Specifications Internal Oscillator Specifications UFM Performance Specifications ADC Performance Specifications
ADC Performance Specifications
Single Supply Devices ADC Performance Specifications Dual Supply Devices ADC Performance Specifications
Periphery Performance Specifications
High-Speed I/O Specifications Memory Standards Supported by the Soft Memory Controller Memory Output Clock Jitter Specifications
High-Speed I/O Specifications
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications True LVDS Transmitter Timing Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Configuration Specifications
JTAG Timing Parameters Remote System Upgrade Circuitry Timing Specifications User Watchdog Internal Circuitry Timing Specifications Uncompressed Raw Binary File (.rbf) Sizes Internal Configuration Time Internal Configuration Timing Parameter
Programmable IOE Delay
Programmable IOE Delay On Row Pins Programmable IOE Delay for Column Pins
Intel® MAX® 10 FPGA Device Datasheet

PLL Specifications

Table 27.  PLL Specifications for Intel® MAX® 10 Devices VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
Symbol Parameter Condition Min Typ Max Unit
fIN   30 Input clock frequency — 5 — 472.5 MHz
fINPFD Phase frequency detector (PFD) input frequency — 5 — 325 MHz
fVCO  31 PLL internal voltage-controlled oscillator (VCO) operating range — 600 — 1300 MHz
fINDUTY Input clock duty cycle — 40 — 60 %
tINJITTER_CCJ  32 Input clock cycle-to-cycle jitter FINPFD ≥ 100 MHz — — 0.15 UI
FINPFD < 100 MHz — — ±750 ps
fOUT_EXT  30 PLL output frequency for external clock output — — — 472.5 MHz
fOUT PLL output frequency to global clock –6 speed grade — — 472.5 MHz
–7 speed grade — — 450 MHz
–8 speed grade — — 402.5 MHz
tOUTDUTY Duty cycle for external clock output Duty cycle set to 50% 45 50 55 %
tLOCK Time required to lock from end of device configuration — — — 1 ms
tDLOCK Time required to lock dynamically After switchover, reconfiguring any non-post-scale counters or delays, or when areset is deasserted — — 1 ms
tOUTJITTER_PERIOD_IO   33 Regular I/O period jitter FOUT ≥ 100 MHz — — 650 ps
FOUT < 100 MHz — — 75 mUI
tOUTJITTER_CCJ_IO  33 Regular I/O cycle-to-cycle jitter FOUT ≥ 100 MHz — — 650 ps
FOUT < 100 MHz — — 75 mUI
tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps
tARESET Minimum pulse width on areset signal. — 10 — — ns
tCONFIGPLL Time required to reconfigure scan chains for PLLs — — 3.5  34 — SCANCLK cycles
fSCANCLK scanclk frequency — — — 100 MHz
Table 28.  PLL Specifications for Intel® MAX® 10 Single Supply DevicesFor V36 package, the PLL specification is based on single supply devices.
Symbol Parameter Condition Max Unit
tOUTJITTER_PERIOD_DEDCLK  33   Dedicated clock output period jitter FOUT ≥ 100 MHz 660 ps
FOUT < 100 MHz 66 mUI
tOUTJITTER_CCJ_DEDCLK  33   Dedicated clock output cycle-to-cycle jitter FOUT ≥ 100 MHz 660 ps
FOUT < 100 MHz 66 mUI
Table 29.  PLL Specifications for Intel® MAX® 10 Dual Supply Devices
Symbol Parameter Condition Max Unit
tOUTJITTER_PERIOD_DEDCLK  33 Dedicated clock output period jitter FOUT ≥ 100 MHz 300 ps
FOUT < 100 MHz 30 mUI
tOUTJITTER_CCJ_DEDCLK  33 Dedicated clock output cycle-to-cycle jitter FOUT ≥ 100 MHz 300 ps
FOUT < 100 MHz 30 mUI
30 This parameter is limited in the Intel® Quartus® Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
31 The VCO frequency reported by the Intel® Quartus® Prime software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
32 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
33 Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
34 With 100 MHz scanclk frequency.
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