Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

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ID 683780
Date 6/14/2022
Public
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6.1.7.4. Timing Closure Guidelines

For the GPIO input registers, the input I/O transfer is likely to fail the hold time if you do not set the input delay chain. This failure is caused by the clock delay being larger than the data delay.

However, if the I/O PLL drives the clocks of the GPIO input registers (simple register or DDIO mode), you can set the compensation mode to source synchronous mode. The Fitter automatically configures the I/O PLL to improve the setup and hold slack for the input I/O timing analysis.

For the GPIO output and output enable registers, you can add delay to the output data and clock using the output and output enable delay chains.

  • If you observe setup time violation, you can increase the output clock delay chain setting.
  • If you observe hold time violation, you can increase the output data delay chain setting.

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