Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 6/14/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.5. GPIO Intel® FPGA IP Architecture

The GPIO IP supports the GPIO components and features of the Intel® Agilex™ device family. You can use the Intel® Quartus® Prime parameter editor to configure the GPIO IP.

Components of the GPIO IP:

  • Double data rate input/output (DDIO)—halves or doubles the data-rate of a communication channel
  • Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure
  • I/O buffers—connect the pads to the FPGA