Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 6/14/2022
Public

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3.3.1. Configuring Open Drain Feature for the HPS I/O

You can turn on the open drain feature for the HPS I/Os through the Hard Processor System Intel® Agilex™ FPGA IP in the Intel® Quartus® Prime Platform Designer.
Figure 24.  Hard Processor System Intel® Agilex™ FPGA IP Parameter Editor


  1. From the Intel® Quartus® Prime menu, select Tools > Platform Designer
  2. Specify the Quartus project and Platform Designer system, then click Open.
  3. In Platform Designer, open the Hard Processor System Intel® Agilex™ FPGA IP parameter editor.
  4. Navigate to the Pin Mux and Peripherals > Pin Mux GUI > Auto-Place IP tab.
  5. Ensure that there are a number of HPS Quantity selected in the GPIO box.
  6. If you make any changes, click Apply Selections, then click OK.
  7. Scroll down to the HPS IO Open Drain Select section.
  8. Turn on the HPS IONN Open Drain Enable that you want.
Figure 25. HPS IO Open Drain Select Section


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